Patent number 8629009 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Programmable memory is being widely used in various electronic applications, such as one-time programmable fuses, field-programmable gate array (FPGA) devices, and programmable logic arrays (PLA). One commonly used programmable memory type is a metal oxide semiconductor field effect transistor (MOSFET) based on hot-carrier effects, in which a high electrical field in the channel of the MOSFET generates hot carriers, which produce electron-hole pairs through impact ionization. Electrons are injected and trapped in the spacer and holes are collected by the substrate. Depending on whether electrons are trapped in the spacer or not, a logic value of '0' or '1' is produced."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A method is provided for integrating programmable memory MOSFETs with logic MOSFETs. Broadly, the method includes providing a semiconductor substrate including a first portion and a second portion; forming a layered gate stack atop the semiconductor substrate, the layered gate stack including a high-k gate dielectric layer atop the semiconductor substrate and a metal electrode layer atop the high-k gate dielectric layer; patterning the metal electrode layer stopping on the high-k gate dielectric layer to provide a first metal gate electrode present in the first portion of the semiconductor substrate, and a second metal gate electrode present in the second portion of the semiconductor substrate; forming a spacer on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric that is not beneath the first metal gate electrode, the second metal gate electrode, and the portion of the high-k gate dielectric that is beneath the spacer is exposed; and etching the remaining portion of the high-k gate dielectric layer to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
"In another aspect, a memory device is provided that includes programmable memory MOSFETs and conventional MOSFETs. Broadly, the memory device includes a semiconductor substrate including a first portion and a second portion; a programmable memory device present in the first portion of the semiconductor substrate including a first gate structure and spacers abutting the first gate structure, the first gate structure including a first metal gate electrode atop a first high-k gate dielectric, wherein a portion of the first high-k gate dielectric is present beneath the spacers; and a semiconductor device present in the second portion of the semiconductor substrate, the semiconductor device including a second gate structure, the second gate structure including a second metal gate electrode atop a second high-k gate dielectric, wherein a sidewall of the second metal gate electrode is aligned to an edge of the second high-k gate dielectric.
"In another aspect, a memory device is provided that includes a gate structure and spacers abutting the gate structure, the gate structure including a metal gate electrode atop a high-k gate dielectric, wherein a portion of the high-k gate dielectric is present beneath the spacers abutting the gate structure."
URL and more information on this patent, see: Booth, Jr., Roger A.; Cheng, Kangguo; Kothandaraman, Chandrasekharan; Pei, Chengwen. Programmable High-K/Metal Gate Memory Device. U.S. Patent Number 8629009, filed
Keywords for this news article include: Electronics, Semiconductor,
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