News Column

Patent Issued for Nonvolatile Memory Devices

January 29, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Lee, Chang-Hyun (Gyeonggi-do, KR); Choi, Jung-Dal (Gyeonggi-do, KR), filed on January 24, 2012, was published online on January 14, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8629489 is assigned to Samsung Electronics Co., Ltd. (KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention is related to semiconductor memory devices and methods of making the same and, more particularly, to nonvolatile memory devices and methods of making the same.

"Nonvolatile memory devices are capable of retaining data that is stored therein even in the absence of a supply of power. Two types of nonvolatile memory devices are NAND and NOR types. A NAND flash memory device has a memory cell string that includes a string selection transistor, pluralities of memory cell transistors, and a ground selection transistor, which are connected with each other in a series circuit. The string selection transistor is connected to a bitline and the ground selection transistor is connected to a common source line.

"In programming the NAND flash memory device, 0V is applied to a selected bitline while a power source voltage of 1.8.about.3.3V is applied to the gate of the string selection transistor, causing a channel voltage of the selected bitline to be set to 0V. A high voltage Vpgm for programming is then applied to a selected wordline so as to carry out a programming operation by means of a Fowler-Nordheim (FN) tunneling effect. During the programming operation, erroneous programming may occur for another memory cell that shares the selected wordline with the selected memory cell but which is connected to the non-selected bitline. In an attempt to prevent such erroneous programming of the adjacent (non-selected) memory cell, an effective technique known as a self-boosting scheme may be used. One approach for inhibiting erroneous programming of a memory cell by use of a self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled 'METHOD OF PROGRAMMING FLASH MEMORY EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN'.

"A self-boosting scheme can include applying 0V to the gate of the ground selection transistor so as to interrupt a current path toward a ground voltage. The power source voltage Vcc is used as a program-inhibiting voltage which is applied to a deselected bitline and the gate of the string selection transistor. Thus, the source of the string selection transistor connected to the deselected bitline is charged up to the level of Vcc-Vth, where Vth denotes a threshold voltage of the string selection transistor. As a result, the string selection transistor is substantially biased in a shut-off state. Then, the selected wordline is supplied a high voltage Vpgm for programming while deselected wordlines are supplied a pass voltage Vpass, which causes a channel voltage of a cell transistor that is not selected for programming is boosted higher. Accordingly, it may be possible to prevent/inhibit programming of deselected memory cells. However, this process may also cause an unacceptable level of leakage current to be generated in a high-density NAND flash memory device.

"For example, with reference to FIG. 1, when a voltage of 0V is applied to a source region 13 and to a gate electrode of the ground selection transistor connected to a deselected bitline, a voltage of a drain region 13' is increased by a boosting action of a channel voltage. Thus, depletion regions 15 around the source and drain regions 13 and 13' may connect with each other to cause a punch-through effect by which a channel current therethrough becomes uncontrollable. The boosted channel voltage may also cause a drain-induced barrier lowering (DIBL) effect. The punch-through and DIBL effects may readily generate leak currents therein, and may complicate the process to inhibit erroneous programming. Such 'soft programming' problems can occur more often as length of the gate electrode becomes shorter (short-channel effects). The continuing trend toward higher integration density for memory devices can therefore lead to greater soft programming problems."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "In accordance with some embodiments of the present invention, a nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

"The second impurity layers having the higher impurity concentration can function to inhibit/prevent leakage current through the associated regions of the string and ground selection transistors, and may thereby avoid malfunction of the memory device during a programming operation.

"In accordance with some other embodiments of the present invention, a nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the string selection transistor and of the ground selection transistor. The second impurity layers are formed at boundaries between the channel and the source region of the string selection transistor and between the channel and the drain region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a lower impurity concentration than the first impurity layers.

"In accordance with some other embodiments of the present invention, a nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor. The first impurity layers are absent from (not formed in) a drain region of a first one of the memory cell transistors that is closest to the string selection transistor or are absent from (not formed in) a source region of a second one of the memory cell transistors that is closest to the ground selection transistor. This may inhibit soft programming effects of the memory cell transistors closest to the string and ground selection transistors due to hot carriers generated by differences between boosting voltages and voltages applied to gates electrodes of the string and ground selection transistors.

"In accordance with some other embodiments of the present invention, a nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor. The first impurity layers are alternatively formed in the source and drain regions of the transistors.

"In accordance with some other embodiments of the present invention, a method of making a nonvolatile memory device includes forming a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor where each has a channel region and source/drain regions in a substrate. First impurity ions are injected into the substrate to form first impurity layers at boundaries of the channels and the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor, the first impurity layers having an opposite conductivity relative to the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor. Second impurity ions, which are same conductivity type as the first impurity ions, are injected into the boundaries between the channel and drain regions of the string selection transistor and between the channel and source regions of the ground selection transistor.

"In some further embodiments, injection of the second impurity ions includes forming an ion implantation mask on the substrate that exposes portions of the drain region of the string selection transistor and the source region of the ground selection transistor, and injecting the second impurity ions into the exposed portions of the drain region of the string selection transistor and the source region of the ground selection transistor.

"In some further embodiments, an interval between the memory cell transistors is L1, a height of the memory cell transistors from the substrate is L2, and the first and second impurity ions are injected at an incident angle .theta.1 defined by .theta.1.gtoreq.tan-1(L2/L1). The second impurity ions can be injected at a smaller incident angle than the first impurity ions. Injection of the second impurity ions can include forming spacers on sidewalls of the string selection transistor, the plural memory cell transistors, and the ground selection transistor, and injecting the second impurity ions into the substrate to form second impurity layers at the boundaries between the channel and drain regions of the string selection transistor and between the channel and source regions of the ground selection transistor.

"In accordance with some other embodiments of the present invention, a method of making a nonvolatile memory device includes forming a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor where each has a channel region and source/drain regions in a substrate. Impurity layers are formed at boundaries of the channels and the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor, except the impurity layers are not formed at the drain region of a first one of memory cell transistors that is closest to the string selection transistor and at the source region of a second one of the memory cell transistors that is closest to the ground selection transistor.

"In accordance with some other embodiments of the present invention, a method of making a nonvolatile memory device includes forming a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor where each has a channel region and source/drain regions in a substrate. First impurity ions are injected into boundaries of the channels and the source regions of the string selection transistor, the memory cell transistors, and the ground selection transistor. The first impurity layers are doped with opposite conductivity type impurities relative to the source regions of the string selection transistor, the memory cell transistors, and the ground selection transistor."

URL and more information on this patent, see: Lee, Chang-Hyun; Choi, Jung-Dal. Nonvolatile Memory Devices. U.S. Patent Number 8629489, filed January 24, 2012, and published online on January 14, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=49&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2436&f=G&l=50&co1=AND&d=PTXT&s1=20140114.PD.&OS=ISD/20140114&RS=ISD/20140114

Keywords for this news article include: High Voltage, Samsung Electronics Co. Ltd.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools