The patent's assignee for patent number 8630143 is
News editors obtained the following quote from the background information supplied by the inventors: "A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store one or more bits of data. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline. Such read and write operations to the given memory cell occur in conjunction with an assertion of its corresponding wordline.
"Memory devices of the type described above may each include one or more memory ports. For example, a single-port random access memory (SPRAM) includes a single memory port and only a single read or write access can be done at a given time through this port. A dual-port random access memory (DPRAM) has two independent memory ports, such that read or write accesses can be performed simultaneously and independently through each port.
"A conventional SPRAM may be a static memory device formed using six-transistor (6T) static
"It is therefore apparent that a need exists for an improved approach to implementing DPRAMs and other multiple-port memory devices."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "A given illustrative embodiment of the present invention overcomes one or more of the drawbacks of the conventional approaches described above at least in part by providing a multiple-port memory device which is implemented using a single-port memory device in combination with control circuitry. By way of example, a dual-port memory device may be provided that is functionally equivalent to an otherwise conventional DPRAM implemented using 8T memory cells, but instead comprises an SPRAM implemented using 6T memory cells and the above-noted control circuitry. The control circuitry in such an arrangement is advantageously configured to provide the desired DPRAM functionality using the SPRAM and its typical array of 6T memory cells. Thus, the overall circuit area and power requirements of the resulting DPRAM are considerably reduced relative to the conventional 8T memory cell approach.
"In one aspect, an apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate.
"Advantageously, the illustrative embodiments provide a DPRAM or other type of multiple-port memory device that can be implemented with lower complexity and reduced cost relative to conventional arrangements.
"A multiple-port memory device in accordance with the invention may be implemented, for example, as a stand-alone memory device, such as a packaged integrated circuit, or as an embedded memory in a microprocessor or other processing device."
For additional information on this patent, see: Nukaraju, Ravikumar; Narasimha, Ashwin. Multiple-Port Memory Device Comprising Single-Port Memory Device with Supporting Control Circuitry. U.S. Patent Number 8630143, filed
Keywords for this news article include: Electronics,
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