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Patent Issued for Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein

January 29, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Lee, Ho-Jin (Seoul, KR); Lee, Kang-Wook (Gyeonggi-do, KR); Park, Myeong-Soon (Seoul, KR); Choi, Ju-il (Gyeonggi-do, KR); Hwang, Son-Kwan (Gyeonggi-do, KR), filed on December 16, 2010, was published online on January 14, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8629059 is assigned to Samsung Electronics Co., Ltd. (KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Efforts to increase the integration density of packaged integrated circuits have frequently included the development of multi-chip modules that can be vertically integrated within single packaged substrate. Techniques to provide vertical integration have frequently included the use of solder bonds between pads and terminals of a plurality of chips that are bonded together in a vertical arrangement. One conventional technique to provide vertical integration is disclosed in US 2002/0109236 to Kim et al., entitled 'Three-Dimensional Multi-Chip Package Having Chip Selection Pads and Manufacturing Method Thereof.' Another conventional technique is disclosed in US 2005/0233581 to Soejima et al., entitled 'Method for Manufacturing Semiconductor Device.' Still further techniques are disclosed in US 2007/0001312 to Murayama et al., entitled 'Semiconductor Chip and Method of Manufacturing the Same.'"

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Methods of forming integrated circuit devices according to embodiments of the present invention include forming vertically extended through-substrate vias as electrical interconnects within a semiconductor substrate. According to some of these embodiments of the invention, a plurality of active semiconductor devices is formed in a semiconductor substrate having top and bottom surfaces thereon. An interlayer dielectric layer is then formed that covers the plurality of active semiconductor devices. This interlayer dielectric layer, which extends on a top surface of the semiconductor substrate, is selectively etched in sequence with the semiconductor substrate to thereby define a through-substrate via extending into the semiconductor substrate. The through-substrate via is then filled with an electrically conductive through-via electrode. This filling of the through-substrate via may be preceded by lining a sidewall of the through-substrate via with a sidewall insulating layer. Thereafter, an intermetal dielectric layer is formed on an upper surface of the interlayer dielectric layer. During formation, this intermetal dielectric layer is formed to have a multi-level metal interconnect therein that contacts the through-via electrode. An electrically conductive contact pad may also be formed on the intermetal dielectric layer. This electrically conductive contact pad is electrically coupled to the multi-level metal interconnect and the through-via electrode. A bottom surface of the semiconductor substrate can be removed to thereby expose the through-via electrode. According to still further embodiments of the present invention, the step of selectively etching the interlayer dielectric layer and the semiconductor substrate in sequence may include selectively etching the interlayer dielectric layer and the semiconductor substrate in sequence to define a through-substrate via having a tapered sidewall that narrows from top to bottom.

"According to additional embodiments of the present invention, a method of forming an integrated circuit device includes forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. Thereafter, the semiconductor substrate is further etched at a bottom of the interconnect hole to thereby define an undercut recess in the semiconductor substrate. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is then planarized for a sufficient duration to expose the uncut recess.

"According to these embodiments of the present invention, the etching step includes isotropically etching the semiconductor substrate at a bottom of the interconnect hole using the first sidewall spacer layer as an etching mask. Moreover, the filling of the interconnect hole may be preceded by removing the first sidewall spacer layer from a sidewall of the interconnect hole. Then, a sidewall of the interconnect hole and the uncut recess can be lined with a second sidewall spacer layer. The planarizing may also include planarizing a second surface of the semiconductor substrate for a sufficient duration to expose the second sidewall spacer layer. This exposure of the second sidewall spacer layer may be followed by selectively etching the exposed second sidewall spacer layer to expose a bulbous end of the through-via electrode that extends outward from the planarized second surface.

"An integrated circuit device according to still further embodiments of the present invention includes a semiconductor substrate having first and second opposing surfaces thereon and a plurality of active semiconductor devices in the first surface. A through-substrate via is provided in the semiconductor substrate. The through-substrate via extends from the first surface to the second surface and has a tapered profile that is wider adjacent the first surface and narrower adjacent the second surface. A through-via electrode is provided in the through-substrate via. The through-via electrode has a length greater than a distance between the first and second surfaces. An intermetal dielectric layer is provided on the first surface and a multi-level metal interconnect is provided, which extends through the intermetal dielectric layer. A first contact pad is also provided on the intermetal dielectric layer. This first contact pad is electrically coupled by the multi-level metal interconnect to the through-via electrode.

"According to these embodiments of the invention, the multi-level metal interconnect includes a plurality of metal wiring patterns at respective levels of metallization and a plurality of electrically conductive plugs that electrically connect the plurality of metal wiring patterns together. In addition, at least one of the plurality of electrically conductive plugs electrically connects the first contact pad to a metal wiring pattern within the multi-level metal interconnect. In still further embodiments of the invention, an interlayer dielectric layer is provided that extends between the intermetal dielectric layer and the first surface. This interlayer dielectric layer is configured so that the through-substrate via extends through the interlayer dielectric layer.

"According to additional embodiments of the invention, an integrated circuit device is provided that includes a semiconductor substrate having a plurality of active semiconductor devices therein extending adjacent a first surface thereof and a second surface extending opposite the first surface. An interlayer dielectric layer is provided, which covers the plurality of active semiconductor devices. In addition, a through-substrate via is provided that extends from an upper surface of the interlayer dielectric layer to the second surface of the semiconductor substrate. A through-via electrode is also provided in the through-substrate via. The through-via electrode has a length greater than or equal to a distance between the second surface of the semiconductor substrate and the upper surface of the interlayer dielectric layer. An intermetal dielectric layer is also provided on the upper surface of the interlayer dielectric layer and a multi-level metal interconnect is provided, which extends through the intermetal dielectric layer. An electrically conductive pad is also provided, which is electrically coupled by the multi-level metal interconnect to the through-via electrode. In some cases, the through-via electrode may include a bulbous extension adjacent the second surface of the semiconductor substrate. The through-substrate via may also be lined with an electrically insulating spacer layer."

URL and more information on this patent, see: Lee, Ho-Jin; Lee, Kang-Wook; Park, Myeong-Soon; Choi, Ju-il; Hwang, Son-Kwan. Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein. U.S. Patent Number 8629059, filed December 16, 2010, and published online on January 14, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=58&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2863&f=G&l=50&co1=AND&d=PTXT&s1=20140114.PD.&OS=ISD/20140114&RS=ISD/20140114

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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