The patent's inventors are Yen, Lee-Sheng (Toayuan, TW); Wang, Doau-Tzu (Toayuan, TW).
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "This invention relates to methods of manufacturing a package substrate, and particularly, to a method of manufacturing a package substrate for use in a miniaturized product.
"With the blooming of the electronic industry, an electronic product generally develops with a compact size, multiple functions and high performance. To meet the miniaturization requirement, a package substrate that is used to carry a chip preferably has a reduced thickness. Currently, the package substrate is made of a hard material or a soft material. For instance, a package substrate used in a ball grid array (BGA) package is made of a hard material.
"Referring to FIGS. 1A to 1C, cross-sectional views illustrating a method of manufacturing a package substrate 1 having two circuit layers according to the prior art are provided.
"As shown in FIG. 1A, two core layers 10 are provided, each of the core layers 10 has a first surface 10a and a second surface 10b opposing the first surface 10a, a first metal layer 11a and a second metal layer 11b are formed on the first surface 10a and the second surface 10b, respectively, and a plurality of through holes 100 connect the first and second surface 10a and 10b.
"As shown in FIG. 1B, a patterning process is performed. Through the first and second metal layers 11a and 11b (using a conductive layer 12 to electroplate metal), first and second circuit layers 13a and 13b are formed on the first and second surfaces 10a and 10b, respectively. Additionally, a conductive via 14 is formed in each of the through hole 100 to electrically connect the first and second circuit layers 13a and 13b. The first and second circuit layers 13a and 13b have a plurality of first and second conductive pads 130a and 130b, respectively.
"As shown in FIG. 1C, first and second insulating protection layers 15a and 15b are formed on the first and second surfaces 10a and 10b of the core layer 10, respectively. The first and second insulating protection layers 15a and 15b have a plurality of first and second openings 150a and 150b, respectively, allowing the first and second conductive pads 130a and 130b to be exposed from the first and second opening 150a and 150b, respectively. Sequentially, first and second surface treatment layers 16a and 16b are formed on the exposed surfaces of the first and second conductive pads 130a and 130b, respectively.
"In subsequent processes, a chip is mounted on the second insulating protection layer 15b, and a molding process is then performed to obtain a package structure. In order to meet the miniaturization and reliability requirements, the core layer 10 has a thickness S reduced to as small as 60 .mu.m.
"However, the core layer 10 having the thickness of 60 .mu.m no longer meets the modern miniaturization requirement. If the thickness S of the core layer 10 is less than 60 .mu.m, the package substrate 1 has a thickness S less than 150 .mu.m. Such a thin package substrate is easily to be damaged during transportation or packaging.
"Therefore, how to solve the problem that the miniaturization is contradictory to the reliability is becoming one of the most popular issues in the art."
Supplementing the background information on this patent, NewsRx reporters also obtained the inventors' summary information for this patent: "In view of the above-mentioned problems of the prior art, the present invention provides a method of manufacturing a package substrate, comprising: providing two core layers, each having a first surface and a second surface opposing the first surface; connecting the two core layers in a manner that the second surfaces of the two core layers are connected by a connection member; forming a first circuit layer on the first surface of each of the core layers; forming a first insulating protection layer on the first circuit layer and the first surface of each of the core layers, with a portion of the first circuit layer exposed from the first insulating protection layer; combining a carrier member with each of the first insulating protection layers by an adhesive layer; removing the connection member to form two substrate bodies, each of which being constituted by the core layer, the first circuit layer, the first insulating protection layer and the carrier member; connecting the carrier members of the two substrate bodies by a combining member, such that the combining member combines the two substrate bodies and the second surface of each of the core layers is exposed; forming a plurality of through holes penetrating each of the core layers from the second surface thereof, with the first circuit layers exposed from the through holes; forming a second circuit layer on the second surface of each of the core layers, and forming in each of the through hole a conductive via for electrically connecting the first and second circuit layers; forming a second insulating protection layer on the second circuit layer and the second surface of each of the core layer, with a portion of the second circuit layer exposed from the second insulating protection layer; and removing the combining member to form two package substrates, each of which being constituted by the core layers, the first and second circuit layer, the first and second insulating protection layers and the carrier member.
"In an embodiment, the carrier members of the two substrate bodies are stacked by a combining member, prior to the formation of the second circuit layers.
"In an embodiment, the adhesive layer is made of a super glue or a release agent, and the carrier member is made of a high-temperature material.
"In an embodiment, on the first and second surfaces of each of the core layers metal layers are formed for being patterned to form the first and second circuit layers, respectively.
"In an embodiment, a surface treatment layer is further formed on the exposed portions of the first and second circuit layers.
"Therefore, in the method of manufacturing a package substrate according to the present invention, a carrier member is combined with a first insulating protection layer of the package substrate, to prevent the package substrate from being damaged during transportation and packaging due to reduced thickness. After the molding process is completed, the carrier member is removed. As a result, the package substrate has a thickness less than 150 .mu.m, and has a reduced overall thickness, as compared to the prior art. Therefore, the package substrate manufactured by the method according to the present invention meets the miniaturization and reliability requirements."
For the URL and additional information on this patent, see: Yen, Lee-Sheng; Wang, Doau-Tzu. Method of Manufacturing a Package Substrate. U.S. Patent Number 8628636, filed
Keywords for this news article include: Treatment, Microtechnology,
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