News Column

Patent Issued for Mask for Forming Integrated Circuit

January 29, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Huang, Richard J. (Cupertino, CA); Bell, Scott A. (San Jose, CA); Dakshina-Murthy, Srikanteswara (Austin, TX); Fisher, Philip A. (Foster City, CA); Nguyen, Richard C. (Fremont, CA); Tabery, Cyrus E. (Sunnyvale, CA); You, Lu (San Jose, CA), filed on September 23, 2011, was published online on January 14, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8629535 is assigned to GlobalFoundries Inc. (Grand Cayman, KY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Deep-submicron complementary metal oxide semiconductor (CMOS) is conventionally the primary technology for ultra-large scale integrated (ULSI) circuits. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry.

"Transistors (e.g., MOSFETs), are often built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions.

"Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (Si.sub.xGe.sub.(1-x)) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. Conventional processes typically utilize polysilicon based gate, conductors because metal gate conductors are difficult to etch, are less compatible with front-end processing, and have relatively low melting points. The transistors can be N-channel MOSFETs or P-channel MOSFETs.

"Generally, it is desirable to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirable to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.

"As critical dimensions (CDs) of device structures are made smaller, certain issues must be addressed during processing. One such issue involves the use of a wet etch to remove mask layers used in the formation of the structures. When structures having small critical dimensions are produced, the introduction of phosphoric acid or other aqueous etchants to remove a mask layer may damage the structure formed during the etching process.

"Another issue that must be addressed is that the shape integrity of the structures formed may be lessened where the materials used to form the mask layer include an internal stress. For example, where a mask material includes an internal compressive or tensile stress by virtue of the microstructure of the material, under certain conditions the mask material may deform. The deformed mask layer will then transfer the deformed pattern into the underlying material when the mask is used during an etch or material removal step. This phenomenon is sometimes referred to as line warpage or 'wiggle.' For example, conductive lines formed, that exhibit warpage or wiggle characteristics may appear as a serpentine or curving structure. The warpage or wiggle of the line may increase the distance that electrons must travel through the conductive line (and hence increase the resistance of the conductive line) when compared to conductive lines that do not exhibit warpage or wiggle characteristics.

"A related issue to the warpage issue described above is the presence of a stress mismatch between certain mask materials and an underlying conductive (e.g., polysilicon, etc.) layer. The internal stress characteristics of the mask material and the conductive layer may result in delamination or warpage of the mask and any features formed in accordance with the mask.

"Thus, there is a need to form structures in an integrated circuit using an improved method that produces structures having reduced critical dimensions. Further, there is a need to improve the shape integrity of structures formed during manufacturing (e.g., reducing or eliminating conductive line warpage, etc.). Even further, there is a need to use amorphous carbon as a mask in the formation of integrated circuit structures. Even further still, there is a need to reduce the amount of stress mismatch between a mask material and an underlying conductive layer that is patterned in accordance with the mask."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An exemplary embodiment, relates to a method of forming an integrated circuit. The method includes providing a buffer layer comprising a dielectric layer above a layer of conductive material. The method also includes providing a layer of mask material comprising amorphous carbon above the buffer layer. The method further includes removing a portion of the buffer layer and the layer of mask material to form a mask and forming a feature in the layer of conductive material according to the mask.

"Another exemplary embodiment relates to a method of forming features in an integrated circuit. The method includes forming a mask above a layer of polysilicon. The mask including a first region comprising a dielectric material, a second region comprising amorphous carbon above the first region, and a third region comprising an anti-reflective coating (ARC) material above the second region. The method also includes forming a feature in the layer of polysilicon according to the mask and removing the mask.

"A further exemplary embodiment relates to an integrated circuit produced by a method that includes providing a conductive material layer above a semiconductor substrate. The method also includes forming a layer of buffer material above comprising a dielectric material above the conductive material layer. The method further includes depositing a layer of amorphous carbon material above the layer of buffer material. The method further includes etching the amorphous carbon layer and the layer of buffer material to form a hard mask and etching the conductive material layer according to the hard mask.

"Other principal features and advantages will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims."

URL and more information on this patent, see: Huang, Richard J.; Bell, Scott A.; Dakshina-Murthy, Srikanteswara; Fisher, Philip A.; Nguyen, Richard C.; Tabery, Cyrus E.; You, Lu. Mask for Forming Integrated Circuit. U.S. Patent Number 8629535, filed September 23, 2011, and published online on January 14, 2014. Patent URL:

Keywords for this news article include: Electronics, Semiconductor, GlobalFoundries Inc..

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Source: Electronics Newsweekly

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