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Researchers Submit Patent Application, "Integrated Circuit Chip and Memory Device", for Approval

January 23, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor KU, Kie-Bong (Gyeonggi-do, KR), filed on December 17, 2012, was made available online on January 9, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to an integrated circuit chip and a memory device, and more particularly, to a technology of testing whether each pad (pin) of an integrated circuit chip has been electrically connected to a substrate (board).

"When an integrated circuit chip such as a memory device is attached to a board, a test is performed to check a bonding state regarding whether bonding of a package has been normally made and pins have been normally connected to the board. The conventional art uses a scheme for testing a bonding state of a board and pins using a test scheme called a boundary scan test. However, since this scheme performs a test by shifting a test pattern, significant time is required.

"In a recent memory device, a connectivity test scheme of simultaneously applying signals to a plurality of pads of a chip and testing an electrical connection state of the pads in a parallel manner has been proposed. In this regard, a chip design that stably supports a connectivity test of new scheme is required."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Exemplary embodiments of the present invention are directed to an integrated circuit chip that ensures a stable operation while supporting a connectivity test scheme of quickly testing an electrical connection state of a plurality of pads on the integrated circuit chip.

"In accordance with an embodiment of the present invention, an integrated circuit chip includes a test enable pad configured to receive a test enable signal, a plurality of test input pads including a reset pad, a signal combination unit configured to combine signals input to the plurality of test input pads when the test enable signal is activated, and to generate a plurality of test output signals, a plurality of test output pads configured to output the plurality of test output signals, and a reset control unit configured to generate a system reset signal using a signal input to the reset pad when the test enable signal is deactivated, and to generate the system reset signal using the test enable signal when the test enable signal is activated.

"In accordance with another embodiment of the present invention, a memory device includes a test enable pad, a reset pad, a chip select pad, a plurality of control pads, a plurality of command pads, a plurality of address pads, a signal combination unit configured to combine signals, which are input to the reset pad, the plurality of control pads, the plurality of command pads, and the plurality of address pads, when a test enable signal input through the test enable pad is activated, and to generate a plurality of test output signals, an output circuit configured to output the plurality of test output signals through a plurality of data pads and a plurality of strobe pads in response to a chip select signal input through the chip select pad, and a reset control unit configured to generate a system reset signal using a signal input to the reset pad when the test enable signal is deactivated, and to generate the system reset signal using the test enable signal when the test enable signal is activated.

"According to the present invention, a reset signal is internally activated in a connectivity test for checking an electrical connection of pads (pins) of an integrated circuit chip, so that a connectivity test operation may be performed after the integrated circuit chip is stably reset.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a diagram illustrating package pins (pads) used in a connectivity test of a memory device.

"FIG. 2 is a block diagram illustrating a memory device in accordance with an embodiment of the present invention.

"FIG. 3 is a detailed diagram illustrating a reception circuit 220 of FIG. 2 in accordance with an embodiment.

"FIG. 4 is a detailed diagram illustrating a reception circuit 220 of FIG. 2 in accordance with another embodiment.

"FIG. 5 is a detailed diagram illustrating a reset control unit 260 of FIG. 2 in accordance with an embodiment.

"FIG. 6 is a timing diagram illustrating an operation of a memory device of FIG. 2 in a connectivity test mode."

For additional information on this patent application, see: KU, Kie-Bong. Integrated Circuit Chip and Memory Device. Filed December 17, 2012 and posted January 9, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4142&p=83&f=G&l=50&d=PG01&S1=20140102.PD.&OS=PD/20140102&RS=PD/20140102

Keywords for this news article include: Sk Hynix Inc.

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Source: Politics & Government Week


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