The assignee for this patent, patent number 8626965, is
Reporters obtained the following quote from the background information supplied by the inventors: "This disclosure generally relates to techniques for testing I/O subsystems in a computing device. More specifically, this disclosure relates to techniques for using a DMA engine to automatically validate DMA data paths and expose any latent bugs or throughput bottlenecks in an I/O subsystem.
"Recent advances in computational technology have led to improved processor capabilities, increased memory sizes, and increasingly sophisticated storage devices and peripherals. However, as the complexity of computer systems grows, comprehensively testing each component becomes difficult, and testing the interactions among multiple components even more so.
"For instance, consider the process of developing and validating a high-performance I/O subsystem. A common challenge in validating an I/O subsystem in a lab is to create sufficient traffic to expose latent bugs or throughput bottlenecks, so that bug fixes or design modifications can be incorporated into the next version of a processor and/or chipset. Unfortunately, creating such traffic intensity can be difficult, because the needed leading-edge I/O devices and device drivers may also still be undergoing testing and may not yet be available. Earlier-generation devices can be used for testing purposes, but they may not generate enough traffic to adequately test a next-generation I/O subsystem. On the other hand, waiting until next-generation devices are available and fully supported potentially delays the discovery of some types of problems.
"Hence, what is needed are techniques for validating an I/O subsystem without the above-described problems."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully.
"In some embodiments, generating sufficient data traffic to exercise the computing device's I/O host interface and DMA data paths involves generating data access patterns that exercise the I/O bandwidth of the computing device to the desired level and confirm memory system coherency for the computing device.
"In some embodiments, the system fully exercises the I/O bandwidth of the computing device to detect a mismatch between functional and performance (e.g., data throughput) capabilities of the computing device's I/O subsystem and the functional and performance capabilities of other (e.g., external) I/O devices which communicate with the computing device. Fully exercising the I/O bandwidth facilitates exposes latent bugs or throughput bottlenecks in the computing device's I/O subsystem.
"In some embodiments, traffic generated by the DMA engine is multiplexed with I/O traffic from one or more external I/O devices.
"In some embodiments, the programmable DMA operation is initiated for a processor in a chip testing environment, where driving and sampling the pins of the processor to exercise the I/O bandwidth of the processor at the desired level might otherwise not be possible.
"In some embodiments, the system configures and initiates the programmable DMA operation by configuring a set of control and status registers for the DMA engine to specify an I/O test pattern and a duration. In some embodiments, this I/O test pattern includes: (1) a revolving pattern of read operations that load a known pattern of distinctive data values from the memory subsystem into a set of data registers in the DMA engine; and/or (2) a revolving pattern of write operations that generate a known pattern of distinctive data values in the DMA engine and transfer them to cachelines in the memory subsystem. Note that this revolving pattern may include unaligned reads and/or writes that trigger read-modify-write sub-operations, thereby stressing the memory and cache coherency subsystem.
"In some embodiments, the computing device may not include a memory device. In such embodiments, the programmable DMA operation may involve sending a pseudo-random stream of data generated in a memory controller to the DMA engine. The DMA engine may then XOR this pseudo-random stream of data into one or more data registers, and then compare a resulting checksum with a known checksum value to confirm that the programmable DMA operation executed successfully."
For more information, see this patent: Feehrer, John R.; Yan, Jane W.; Noel, Matthew G.. Using a DMA Engine to Automatically Validate DMA Data Paths. U.S. Patent Number 8626965, filed
Keywords for this news article include: Information Technology, Information and Data Traffic,
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