Patent number 8624668 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Current-sensing amplifiers output a voltage proportional to an input current. They may use a resistor to convert the input current into a corresponding voltage, which is then amplified. Among many other applications, current-sensing amplifiers may be used for motor and solenoid control in, for example, automotive power-steering and adaptive-suspension systems, industrial-process control, and medical applications. FIGS. 1A and 1B illustrate diagrams of solenoid 100 and motor control 150 applications, respectively. In such applications, the input 102 receives a pulse-width modulated waveform 104 that toggles between (for example) -2 V and 24 V, 48 V, or 80 V. The rising and falling time of the transitions of the input 102 may be as small as approximately 10 nS, and the frequency of the input 102 may be as great as approximately 20 kHz. A current-sensing amplifier 106 in such applications may be judged on the offset (i.e., a difference between real and expected output values), drift (i.e., a change in output values despite constant input values), and common-mode step response of its output. Ideally, the amplifier 106 produces a result based on the difference between its inputs, regardless of the actual values of the inputs (i.e., their common-mode level); in practice, however, the output of the amplifier 106 may change at different common-mode levels of its inputs. For example, if the amplifier 106 is tuned to remove an offset at a first common-mode level, the tuning may need to be adjusted at a second common-mode level to remove a new offset introduced by the new common-mode level.
"The common-mode step response of the amplifier 106 may be especially important in applications having large changes in the input common mode voltage; while the amplifier 106 is recovering from the change in input common mode voltage, the output of the amplifier may not be valid due to the new offset induced by the new common-mode level. Thus, a long settling time of the amplifier 106 (and thus the large error during that period of time) may seriously degrade the dynamic performance of the amplifier 106. In addition, such amplifiers typically have an unacceptably large DC offset, offset drift, and poor CMRR, thus making them unsuitable for precision applications.
"In order to improve the DC precision of the amplifier, an auto-zero technique may be used. FIG. 2 illustrates an example of a 'ping-pong' auto-zero amplifier 200. It has two input paths 202, 204 disposed in parallel: each path 202, 204 includes a main amplifier 206, an auxiliary differential pair 208 to correct the offset of the main amplifier, and a pair 210 of offset-storage capacitors. The offset-storage capacitors 210 sample the voltage on the outputs 212 of the main amplifiers 206 and feed the samples back, via the auxiliary differential pairs 208, to tuning the main amplifiers 206 to correct any offset therein. Each path 202, 204 may be calibrated periodically and alternatively, in accordance with, for example, an auto-zero clock, so that the offset-correction voltage is refreshed periodically. In other words, while one path 202 is amplifying the input signal, the other path is calibrating itself, and vice-versa. Such an auto-zero amplifier 200 may achieve very low DC offset, offset drift, and high DC CMRR.
"It may take a relatively long time, however, for a traditional auto-zero amplifier to recover (i.e., cancel a new offset) after a step in the input common-mode voltage and, during recovery, the output of the amplifier may be invalid. An offset in an amplifier may result from a mismatch between devices' transconductance and/or mismatching between devices' output impedance. The degree of mismatching may be affected by device bias current, MOSFET drain-to-source voltage and back-gate bias voltage, and/or bipolar transistor collector-to-emitter voltage. All of these factors may be affected by input common mode voltage. Because the amplifier typically has different offsets at different common-mode voltages, and thus requires different offset-correction voltages to correct these offsets, this long recovery time hinders the accuracy of the amplifier. The recovery time varies significantly: it may depend on the unpredictable timing relationship between the auto-zero cycle and input common mode step and/or the auto-zero clock frequency, which varies with temperature and process corner. In other words, if a sudden step in the input common-mode voltage occurs at a first time t.sub.0 and creates an offset in the output of the auto-zero amplifier, it may not be corrected until a later time t.sub.1 during the next auto-zero cycle. The times t.sub.0 and t.sub.1, and the length of time between them, may be unknown and unpredictable. Although the auto-zero frequency may be increased to reduce the length of such time, nevertheless, due to the discrete nature of auto-zero operation, the amplifier is still unable to start the settling process immediately after a common mode input step. Furthermore, in practice, the settling time of the auto-zero calibration loop, power consumption, switch charge injection, etc., may limit how fast the auto-zero frequency can be. Other techniques used to improve the DC accuracy of a current-sensing amplifier, such as chopper stabilization, have the same drawbacks due to, for example, the long settling time of a capacitor in an internal filter.
"FIG. 3 illustrates a common-mode step response 300 of a traditional ping-pong auto-zero amplifier as a function of time 302 (in microseconds). An input common-mode voltage 304 toggles between a wide common-mode range (in this example, between -2 V 306 and 80 V 308, but the invention is not limited to these values); an auto-zero control logic signal 310 toggles between high 312 and low 314 values to enable and disable two paths of a ping-pong amplifier (such as the paths 202, 204 described above with reference to FIG. 2). When the control signal 310 is at logic high 312, a first ping-pong main amplifier is in auto-zero mode and the a second ping-pong main amplifier is in the signal path; conversely, when the control signal 310 is at logic low 314, the second ping-pong main amplifier is in auto-zero mode and the first ping-pong main amplifier is in the signal path. The output 300 of the overall amplifier is, in this example, configured to have a gain of 20.
"As is shown in FIG. 3, the settling times 316, 318 of the output 300 in response to the transitions in the common-mode input 304 may be long and unpredictable. For example, at approximately 29 uS, the common-mode voltage 304 steps from 80 V down to -2V, and a large offset appears at the amplifier output 300; this offset persists until approximately 35 uS. The offset persists for so long because of the timing of the input step 304 and the auto-zero control 310. Between 29 uS and 30 uS, the first ping-pong main amplifier is in the signal path; its offset-correction voltage was calibrated, during its auto-zero mode, at a common-mode voltage of 80 V. Between 26.5 uS and 30.5 uS, the second main amplifier is in auto-zero mode. At 29 uS, however, the common-mode input 304 suddenly changes, which also changes the offset of the first and second main amplifiers. Between 29 uS and 30.5 uS, a very large error 320 (e.g., >150 mV) appears at the output 300 due to the sudden offset change of the first main amplifier resulting from the large change in the common-mode level of the input 304. During the same time, the second main amplifier also tries to find the new offset-correction voltage for the new common mode level; it has only 1.5 uS to do so, however. The second main amplifier does thus not have enough time to settle to the correct offset-correction voltage by the end of its auto-zero cycle. At 30.5 uS, the second main amplifier switches from auto-zero mode into the signal path, producing an undesirable offset 322 (e.g. a bump riding on the output 300) between approximately 30.5 uS and 35 uS. The output 300 finally settles at its correct value at 35 uS, after the first main amplifier is in auto-zero mode at -2V between 30.5 uS to 35 uS and then switches back into the signal path. The total common mode step recovery time is thus 6 uS. The next common-mode step happens at 54 uS; in this case, the overall recovery time is about 4 uS for similar reasons.
"Thus, existing current-sensing amplifiers may not properly handle large steps in input common mode voltage. A need therefore exists for a cost-effective and precise way to compensate for large and/or fast changes in an input common-mode voltage."
In addition to the background information obtained for this patent, NewsRx journalists also obtained the inventors' summary information for this patent: "In general, various aspects of the systems and methods described herein include improving the settling time of an auto-zero amplifier. An offset-storage device (e.g., a capacitor for a single-ended implementation, a capacitor pair for a differential implementation, or a digital-register array if a corresponding offset-correction voltage has been converted into a digital format by analog to digital converters) is used for steady-state operation. One or more additional offset-storage devices are connected via a switching and control network to the offset-correction circuit; at least one additional offset-storage device (e.g., capacitor, capacitor pair, or digital resister array) is charged to a voltage corresponding to a level of the input common mode voltage after a step therein. The additional offset-storage device is switched to replace the steady-state offset-storage device after a step in the input voltage is detected and thereby settles the voltage of the amplifier more quickly. The amplifier may be an auto-zero amplifier or any other amplifier that may be subjected to an input common-mode voltage having large steps and that implements either an internal auto-offset adjustment or externally applied adjustment. Furthermore, the offset adjustment is not limited to implementation in the analog domain. In one embodiment, the offset corresponding each common mode input level may be converted to a digital format by an analog-to-digital converter, stored in digital register arrays, and converted back into analog to cancel the offset of the amplifier by a digital-to-analog conversion circuit. In other embodiments, the output of the amplifier may be converted to one or more digital signals, and the offset-correction may be done completely in the digital domain with digital register arrays that store an offset-correction voltage corresponding to each common mode input level during calibration mode.
"In one aspect, a system for improving common-mode response of an auto-zero amplifier includes a first offset-storage element for storing a first value corresponding to a first common-mode level of an input signal and a second offset-storage element for storing a second value corresponding to a second common-mode level of the input signal. A main amplifier amplifies the input signal; it receives an offset-correction signal, generated based on the first value, for cancelling an offset at the first common-mode level. Control logic detects a transition in the input signal from the first common-mode level to the second common-mode level, and a switch (upon detection of the transition) severs a first connection to the first offset-storage element and creates a second connection to the second offset-storage element, thereby generating the offset-correction signal using the second value instead of the first value.
"In various embodiments, the first and second offset-storage elements are capacitors or digital registers. The switch may sever and create the first and second connections immediately upon detection of the transition when the main amplifier is in a signal-path mode and/or during a next transition of an auto-zero clock when the main amplifier is in an auto-zero mode. The auto-zero amplifier may be a ping-pong auto-zero amplifier. The main amplifier, first and second steady-state offset-storage elements, control logic, and switch may comprise one of two paths in the ping-pong auto-zero amplifier; the system may further include a second path comprising a second main amplifier, second first and second offset-storage elements, a second control logic, and a second switch. An auto-zero clock may be used for switching between the first path and the second path.
"A third offset-storage element may store a third value corresponding to the first common-mode level of the input signal; the control logic may detect a second transition in the input signal from the second common-mode level back to the first common-mode level, and the switch may sever the first or second connections and create a third connection to the third offset-storage element. An auxiliary differential pair may generate the offset-correction signal in accordance with the values of the first or second offset-storage elements.
"The system may further include (i) a first auxiliary differential pair for generating the offset-correction signal, in accordance with the value of the second offset-storage element, for low-to-high transitions of the common-mode level of the input signal and (ii) a second auxiliary differential pair for generating the offset-correction signal, in accordance with a value of a third settling offset-storage element, for high-to-low transitions of the common-mode level of the input signal. A third auxiliary differential pair may generate the offset-correction signal, in accordance with the value of the first offset-storage element, during a steady-state of the common-mode level of the input signal.
"In another aspect, a method for improving common-mode response in an auto-zero amplifier includes generating an offset-correction signal for correcting an offset in a main amplifier; the offset-correction signal depends at least in part on a first value corresponding to a first common-mode level of an input signal. A change in the common-mode level of the input signal from the first common-mode level to a second common-mode level is detected, and (upon detection) the first value is switched for a second value previously stored for the second common-mode voltage level, thereby modifying the offset-correction signal. The modified offset-correction signal is applied to the main amplifier to thereby cancel a new offset introduced by the change in the common-mode level.
"In various embodiments, the method further includes (i) detecting a second change in the input common-mode level of the signal input from the second common-mode level back to the first common-mode level, (ii) switching, in response to the detected second change, the first or second value with a third value previously stored for the first common-mode voltage level; and (iii) applying the modified offset-correction signal to the main amplifier to thereby cancel a new offset introduced by the second change in the common-mode level. The switching may occur immediately after detecting the change if the main amplifier is in a signal-path mode or after a next transition in an auto-zero clock if the main amplifier is in an auto-zero mode. The second offset-storage element may be disconnected prior to the input common-mode voltage changing from the second voltage level. The first and second values may be stored in capacitors or digital registers, and the second value may be stored prior to the detected change. The storing of the second value may occur during an auto-zero mode.
"These and other objects, along with advantages and features of the present invention herein disclosed, will become more apparent through reference to the following description, the accompanying drawings, and the claims. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations."
URL and more information on this patent, see: Wan, Quan; Alexander, Alasdair G.. Common-Mode Step Response for Autozero Amplifiers. U.S. Patent Number 8624668, filed
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