The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a 'design flow.' The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware 'tools' verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
"Several steps are common to most design flows for integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as 'functional verification.'
"After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices, such as transistors, resistors, and capacitors, which will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as 'formal verification.'
"Once the relationships between circuit devices have been established, the design can be again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a 'layout' design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.
"Typically, a designer will perform a number of analyses on the resulting layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc. For example, the design flow process may include one or more resolution enhancement technique (RET) processes, that modify the layout design data to improve the usable resolution of the reticle or mask created from the design in a photolithographic manufacturing process.
"After the layout design has been finalized, it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. The written masks or reticles then can be used in a photolithographic process to expose selected areas of a wafer to light or other radiation in order to produce the desired integrated microdevice structures on the wafer.
"Returning to 'functional verification,' this type of analysis begins with a circuit design coded at a register transfer level (RTL), which can be simulated by a design verification tool. A designer, for example, utilizing the design verification tool, can generate a test bench that, when input to the simulated circuit design, can allow the design verification tool to analyze the functionality of the simulated circuit design. When the simulated circuit design operates differently than expected in response to the test bench, the designer can attempt to debug the circuit design, for example, to determine which of the gates in the circuit design is incorrectly configured, resulting in the generation of illegal states or transitions.
"The design verification tool can record signal states and transitions of the circuit design, often called waveform data, which the designer can review in an attempt to identify a 'bug' in the circuit design. The designer typically can utilize a debug tool to review the recorded waveforms, often alongside a source code of the circuit design, in an attempt to locate and address the circuit design failure.
"Often, however, the simulated circuit design can operate differently than expected, not due to a 'bug' in the circuit design, but due to a defect in the test bench, for example, incorrect stimulus being applied to the simulated circuit design, improper response checking, or both. Thus, the designer may attempt to review test bench states and transitions, a source code of the test bench, a source code of the circuit design, and the waveform data, often in unison, to ascertain whether the verification failure was the result of a 'bug' in the circuit design, a test bench defect, or both.
"Since many test benches are generated with object-oriented programming languages that are transient in nature, for example, with object components, such as classes, being created and destroyed during execution, test bench states and transitions are recorded separately from and in a different format than the waveform data of the simulated circuit design, leaving designers to manually collate test bench states and transitions with the waveform data."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "This application discloses tools and mechanisms for simulating a circuit design with a test bench, performing functional verification on the simulated circuit design, and, when functional verification fails, preparing data from operation of both the circuit design and test bench during the simulation. In some embodiments, a design verification tool can simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.
DESCRIPTION OF THE DRAWINGS
"FIGS. 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments of the invention.
"FIG. 3 illustrates an example system including a design verification tool and a debug tool that may be implemented according to various embodiments of the invention.
"FIG. 4 illustrates a flowchart showing an example implementation of test bench transaction synchronization with waveform data and/or test bench source code according to various examples of the invention.
"FIG. 5 illustrates a flowchart showing an example implementation of test bench transaction extraction from a simulation log according to various examples of the invention.
"FIG. 6 illustrates an example simulation log display window according to various embodiments of the invention.
"FIG. 7 illustrates an example waveform display window according to various embodiments of the invention.
"FIG. 8 illustrates an example test bench source display window according to various embodiments of the invention.
"FIG. 9 illustrates a flowchart showing an example implementation of synchronization between a simulation log display window and a waveform display window according to various examples of the invention.
"FIG. 10 illustrates a flowchart showing an example implementation of synchronization between a test bench transaction display window and a test bench source display window according to various examples of the invention."
For more information, see this patent application: AGARWALA, BADRUDDIN; Parikh, Tarak; Bhat,
Keywords for this news article include: Software,
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