Argon Design, a design services company specializing in complex digital systems has developed a high performance trading system using a heterogeneous mix of technologies to minimize trading latency.
Working with Arista Network's 7124FX Application Switch which includes an Altera FPGA with hardware-level access to 8 of its 24 10Gb Ethernet ports and an x86 domain based on
The enhancement in performance was achieved by providing a fast-path where trades are executed directly by the FPGA under the control of trigger rules processed by the x86 based functions. The latency is reduced further by two additional techniques in the FPGA – inline parsing and pre-emption.
As market data enters the switch, the Ethernet frame is parsed serially as bits arrive, allowing partial information to be extracted and matched before the whole frame has been received.
Then, instead of waiting until the end of a potential triggering input packet, pre-emption is used to start sending the overhead part of a response which contains the Ethernet, IP, TCP and FIX headers. This allows completion of an outgoing order almost immediately after the end of the triggering market feed packet.
The overall effect is a dramatic reduction in latency to close to the minimum that is theoretically possible.
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