By Targeted News Service
ALEXANDRIA, Va., Sept. 26 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,543,952) developed by Vinod Kariat, Sunnyvale, Calif., Eddy Pramono, Santa Clara, Calif., and Yong Zhan, Milpitas, Calif., for a "method and apparatus for thermal analysis of through-silicon via (TSV)."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit ("IC") design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via ("TSV"). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments."
The patent application was filed on Nov. 4, 2011 (13/290,047). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,543,952.PN.&OS=PN/8,543,952&RS=PN/8,543,952
Written by Kusum Sangma; edited by Anand Kumar.