By Targeted News Service
ALEXANDRIA, Va., Sept. 18 -- Agere Systems, Wilmington, Del., has been assigned a patent (8,539,423) developed by Joseph J. Jamann, Allentown, Pa., James C. Parker, Allentown, Pa., and Vishwas M. Rao, Milpitas, Calif., for a "systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage."
The patent application was filed on Oct. 11, 2012 (13/649,996). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8539423.PN.&OS=PN/8539423&RS=PN/8539423
Written by Kusum Sangma; edited by Anand Kumar.