No assignee for patent application serial number 779464 has been made.
News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to an electrostatic discharge protection circuit for an integrated circuit, and to an integrated circuit comprising such a protection circuit.
"An integrated circuit (IC) comprising sensitive internal circuitry may be subjected to an Electrostatic Discharge (ESD) event consisting of a very high voltage applied to pins or pads of the circuit. Such an event may damage the circuitry and occur during the manufacture, assembly, testing, or normal handling and operation of the integrated circuit or of a product in which the integrated circuit is incorporated. Clamp circuits or 'shunts', such as a large MOSFET transistor, are therefore commonly provided as part of an ESD protection circuit to couple power and ground supply rails of the IC in response to a detection of an ESD event. The high voltage received is thereby dissipated through the shunt and the sensitive circuitry is protected from damage.
"FIG. 1 shows a conventional integrated circuit IC comprising an ESD protection circuit EC along the lines of the circuit disclosed by U.S. Pat. No. 5,946,177. The integrated circuit comprises a voltage pad PV coupled to a power supply rail PSR, a ground pad PG coupled to a ground supply rail GSR, and an input/output pad P0. The integrated circuit IC further comprises internal circuitry CT and an ESD protection circuit EC, both linked to the supply rails PSR, GSR.
"The ESD protection circuit EC comprises an input 1, a trigger 2, a trigger output node N3, a delay 3, and a shunt transistor TN1 configured to couple the rails PSR, GSR of the integrated circuit IC. Input 1 comprises an input node N1 and diodes D1, D2. Input node N1 is coupled to the pad P0 and to the supply rails PSR, GSR via diodes D1, D2 respectively. As diodes D1, D2 are on the ESD discharge path, they are relatively large.
"The trigger 2 comprises a resistor R1 and a capacitor C1 in series forming an RC transient filter, a detection node N2, and a PMOS transistor TP1. Resistor R1 has one terminal coupled to the power supply rail PSR and one terminal coupled to node N2. The capacitor C1 has one terminal coupled to node N2 and one terminal coupled to the ground supply rail GSR. Transistor TP1 has a gate terminal G driven by node N2, a source terminal S coupled to the power supply rail PSR, and a drain terminal D coupled to the trigger output node N3.
"The delay 3 comprises a resistor R2 and a capacitor C2. Resistor R2 and capacitor C2 each have one terminal coupled to node N3 and one terminal coupled to the ground supply rail GSR. Capacitor C2 may be a gate-body parasitic capacitance of transistor TN1 or a physical capacitor. Finally, the shunt transistor TN1 has a control terminal (gate terminal G) driven by node N3, a drain terminal D coupled to the power supply rail PSR, and a source terminal S coupled to the ground rail GSR.
"Circuit EC provides protection from positive ESD events applied between pad PV and a grounded pad PG, negative ESD events applied between pad PG and a grounded pad PV, as well as ESD events between pad P0 and either of pads PV, PG.
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