The patent's assignee for patent number 8525268 is
News editors obtained the following quote from the background information supplied by the inventors: "In power management applications, co-packaging an integrated circuit with a discrete semiconductor device such as a discrete power device of metal oxide semiconductor field effect transistor ('MOSFET'), junction field effect transistor ('JFET'), or other devices has become a major trend for cost and size saving. In most high voltage and/or large current power management applications, a vertical discrete transistor such as a vertical power transistor of vertical MOSFET, vertical JFET or field effect transistor ('FET') with integrated Schottky diode is often used and co-packaged with its integrated control circuit to achieve high power management performance while reducing cost and package size.
"Conventionally, a semiconductor die of vertical power MOSFET, JFET, FET with an integrated Schottky diode or other vertical transistors typically comprise a drain/cathode electrode on a bottom surface and source and gate electrodes on a top surface. In many power management applications, an N-type vertical transistor is configured as a low-side switch, meaning that the source electrode is connected to the lowest potential (i.e. ground) and an electrical load is connected between the drain electrode and a higher potential (i.e. VDD). When the MOSFET is switched on and off (by modulation of the gate-source voltage), the source voltage stays relatively constant, while the drain voltage alternates between high and low voltages. Since the drain electrode is on the bottom surface of the MOSFET die, it is typically connected to the leadframe of a package. For high-power devices, the leadframe is exposed for better thermal performance. The presence of high and transitioning voltage on the exposed leadframe is often undesirable because it requires electrical isolation and can be a source of radiated electromagnetic interference ('EMI').
"Prior art co-package solutions (i.e., a control chip and a vertical MOSFET in the same package) use vertical MOSFET devices that have backside drain. The high and transient voltage on the drain causes isolation and EMI problems as described above. Moreover, since the MOSFET drain is at a different voltage than the substrate of the control chip, they may not be electrically connected to the same leadframe. One prior art solution uses a non-conductive epoxy to attach the control chip to the leadframe. This provides the needed isolation, but compromises the thermal performance (i.e., the ability of the package to dissipate heat produced in the control chip). Another approach uses a special package with a split leadframe, one piece under the control chip and a separate (and isolated) piece under the MOSFET. This increases packaging cost and can complicate the attachment of the package to a print circuit ('PC') board."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "In one embodiment, a vertical semiconductor device comprises a substrate comprising a drain and a first surface and a second surface opposite to the first surface; an epitaxial layer formed on the first surface of the substrate and having a third surface opposite to the first surface of the substrate; a source region formed in the epitaxial layer adjacent to the third surface; a gate formed adjacent to the source region; a source electrode coupled to the source region and isolated from the gate; a drain electrode formed on the second surface of the substrate and coupled to the drain; a first gate electrode formed adjacent to the second surface of the substrate; and a deep gate contact coupling the gate to the first gate electrode. The first gate electrode is isolated from the substrate.
"In another embodiment, a method of manufacturing a semiconductor device comprises providing a substrate of a first conductivity type. The substrate has a first surface and a second surface opposite to the first surface. The method also includes growing an epitaxial layer on the first surface of the substrate, and the epitaxial layer has a third surface opposite to the first surface of the substrate. The method further includes forming a gate in the epitaxial layer, forming a source region of the first conductivity type adjacent to the gate, and forming a source electrode. The source electrode is coupled to the source region and is isolated from the gate. The method yet further includes forming a drain electrode on the second surface of the substrate and forming a first gate electrode adjacent to the second surface of the substrate. The first gate electrode is isolated from the substrate. The method also includes forming a deep gate contact that couples the gate to the first gate electrode."
For additional information on this patent, see: Disney, Donald R.. Vertical Discrete Device with Drain and Gate Electrodes on the Same Surface and Method for Making the Same. U.S. Patent Number 8525268, filed
Keywords for this news article include: Electronics, Semiconductor,
Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2013, NewsRx LLC
Most Popular Stories
- NSA Defends Global Cellphone Tracking Legality
- Ad Counts Rise in 2013 for Hispanic Magazines
- Top Websites for U.S. Hispanics
- Networks Vie for U.S. Hispanic TV Viewers
- Saab Gets Back into the Game; U.S. Auto Sales Soar
- Apple Activates Customer-Tracking iBeacon
- Dell Offers Undisclosed Number of Employee Buyouts
- Authorities Close to Deal with JPMorgan Chase over Madoff Response
- 2013 Tech Gift Guide: iPad Mini Still Hot; Chromecast a Great Low-Cost Option
- A Biography of Jonathan Ive, Apple's Creative Chief