Patent number 8526078 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a sensor driving circuit, a sensor driver device, an image reading apparatus, and an image forming apparatus capable of decreasing influence of skew among signals having different edges.
"Charge-coupled device (CCD) line image sensors (hereinafter, referred to as 'CCD') have been employed in an image reading apparatus as photoelectric converter for reading images of an original. There may be cases where variation in threshold voltages, and difference in delay time of rise time (hereinafter, 'rise delay time') and in delay time of fall time (hereinafter, 'fall delay time') of a CCD driver that drives the CCD and variation in the difference are not negligible, making it difficult to secure timing appropriately. To this end, techniques of supplying signals, on which timing is stipulated, via a single same driver so as to reduce timing variation (skew) and to secure signal timing have already been known.
"For instance, Japanese Patent Laid-open Publication No. H11-177783 discloses a configuration, in which a drive signal, which serves as reference for timing of output signals of a CCD (hereinafter, 'CCD output signal'), and an output signal of a sample-and-hold circuit (hereinafter, 'sample/hold signal') in an analog-front-end (AFE) are supplied via a single driver so as to reduce skew between the CCD output signal and the sample/hold signal.
"An example of a driving circuit according to a conventional technique is described below.
"FIG. 10 is a functional block diagram of a conventional driving circuit that drives a CCD 2 and an AFE 3.
"A timing generator (TG) 1 generates various clock signals and gate signals required by the CCD 2 and the AFE 3. A CCD-drive clock signal xCCD_clk, which is one of the output signals of the TG 1, is inputted to the CCD 2 via a CCD driver (hereinafter, 'DRV') 4. Because an inverting driver, which is advantageous in terms of speed, is typically used as the DRV 4, an output signal CCD_CLK of the DRV 4 is inverted relative to the CCD-drive clock signal xCCD_clk in the configuration illustrated in FIG. 10. The CCD 2 outputs an analog image signal SIG. After being buffered in an emitter follower (EF) 5, the analog image signal SIG is inputted to the AFE 3 via a coupling capacitor 6.
"The AFE 3 conducts sampling-and-holding, clamping, offset correction, signal amplification, and the like on the analog image signal SIG and the analog image signal SIG is eventually subjected to analog-to-digital (A/D) conversion. The digital image data D is outputted from the AFE 3. Meanwhile, a sample/hold signal SHD supplies a signal xshd that is outputted from the TG 1 to the AFE 3 via the DRV 4.
"The sample/hold signal SHD is inverted relative to the signal xshd as in the case described above. The sample/hold signal SHD may not necessarily need to pass through the DRV 4; however, in order to reduce skew between an output signal of the CCD (whose output timing depends on the signal COD_CLK) and the sample/hold signal SHD, the sample/hold signal SHD and the output signal of the CCD are supplied via the same driver in this configuration.
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