The patent's inventors are Min,
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to selecting chips within a stacked semiconductor package using through-electrodes.
"In the semiconductor industry, packaging technologies for integrated circuits have continuously been developed to satisfy the demand toward miniaturization and mounting reliability. Recently, as miniaturization and high performance in demand for electric and electronic products, various stacking techniques have been developed.
"The term 'stack' that is referred to in the semiconductor industry means to vertically place together at least two semiconductor chips or semiconductor packages. In the case of a memory device, by using stacking technology, it is possible to realize a product having memory capacity at least two times greater than without stacking. Since stacked semiconductor packages have advantages in terms of not only memory capacity but also mounting density and mounting area utilization efficiency, research and development for stacked semiconductor packages have accelerated.
"Use of through-electrodes have been proposed for stacked semiconductor packaging. For this type of package, through-electrodes are formed in semiconductor chips such that the semiconductor chips can be electrically connected by the through-electrodes."
Supplementing the background information on this patent, NewsRx reporters also obtained the inventors' summary information for this patent: "Embodiments of the present invention are directed to a stacked semiconductor package which uses through-electrodes.
"In one embodiment of the present invention, a stacked semiconductor package includes: first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units; and a spacer including a spacer body which is interposed between the first semiconductor chip and the second semiconductor chip, an inverter chip which is embedded in the spacer body, and wiring patterns which are formed on the spacer body and connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip.
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