Patent number 8525993 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Scatterometry has been used extensively for the characterization of critical dimensions (CD) and detailed side-wall profiles of periodic structures in microelectronics fabrication processes. Scatterometry can provide accurate and high-precision measurement for 2D and 3D structures used in integrated circuits. Various experimental configurations, e.g., normal incident broadband reflectance spectroscopy, spectroscopic ellipsometry, and angular scatterometry measurement, have been developed to collect light signals diffracted from periodic structures. So far the majority of measurements were applied for symmetric gratings. In most cases devices are designed to be symmetric although errors could occur during fabrication processing and result in undesired asymmetry.
"One example of asymmetry is alignment or overlay error. Typically, overlay targets are used to determine if the pattern produced in one layer is adequately aligned with the pattern in an underlying or previously patterned layer. However, as integrated circuit feature size continues to decrease to provide increasing circuit density, it becomes increasingly difficult to accurately measure the overlay between successive layers. This overlay metrology problem becomes particularly difficult at submicrometer feature sizes where overlay tolerances are reduced to provide reliable semiconductor devices.
"FIG. 1 illustrates a conventional box-in-box overlay target 2 used with conventional image based overlay metrology methods. Target 2 is formed by producing an etched box 4 in first material layer on a substrate and another box 8 in a second material layer, or on the same layer. The target 2 is produced on the wafer off the chips, e.g., in the scribe lines between chips. The overlay target 2 is imaged to determine whether the second layer is properly aligned with the first layer. Other image based overlay targets, such as a bar-in-bar target, are produced and imaged in a similar fashion. Conventionally, high magnification imaging is used to measure image based overlay targets, such as target 2. Conventional imaging devices, unfortunately, suffer from disadvantages such as lack of sensitivity to vibration and cost. Moreover, conventional imaging devices suffer from a trade-off between depth-of-focus and optical resolution. Additionally, edge-detection algorithms used to analyze images for the purpose of extracting overlay error are inaccurate when the imaged target is inherently low-contrast or when the target suffers from asymmetries due to wafer processing. The existing method of image-based overlay is expected to reach its limit soon due to deviations from the actual device overlay error within the die. Image based overlay targets are outside the chip, e.g., in a scribe line and are larger scale than most current and future devices. Consequently, the overlay errors measured by image based overlay targets are not suitable to represent the true overlay error in the actual device area.
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