By Targeted News Service
ALEXANDRIA, Va., Aug. 28 -- Syntest Technologies, Sunnyvale, Calif., has been assigned a patent (8,522,096) developed by five co-inventors for a "method and apparatus for testing 3D integrated circuits." The co-inventors are Laung-Terng Wang, Sunnyvale, Calif., Nur A. Touba, Austin, Texas, Michael S. Hsiao, Blacksburg, Va., Zhigang Jiang, Burlingame, Calif., and Shianling Wu, Princeton Junction, N.J.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss."
The patent application was filed on Aug. 31, 2011 (13/222,130). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,522,096.PN.&OS=PN/8,522,096&RS=PN/8,522,096
Written by Kusum Sangma; edited by Anand Kumar.