By Targeted News Service
ALEXANDRIA, Va., Aug. 26 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,513,113) developed by Steven Oliver, Boise, Idaho, and Warren M. Farnworth, Nampa, Idaho, for "methods of forming semiconductor constructions and assemblies."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies."
The patent application was filed on Oct. 19, 2009 (12/581,586). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,513,113.PN.&OS=PN/8,513,113&RS=PN/8,513,113
Written by Kusum Sangma; edited by Anand Kumar.