The patent's assignee for patent application serial number 751549 is
News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to the protection of an integrated circuit chip against laser attacks.
"In certain secure devices such as payment cards, integrated circuits chips are likely to process and/or store critical data, for example, encryption keys. Such chips may be fraudulently manipulated to obtain protected confidential data.
"To intentionally cause disturbances in the circuits of a chip, an attack mode comprises bombarding chip areas with a laser beam while the chip is operating. Due to the presence of interconnection metal tracks on the front surface side of the chip, laser attacks are often carried out on the back side.
"To avoid frauds, chips comprising attack detection devices have been provided. The attack detection device is coupled to a chip protection circuit. When an attack is detected, the protection circuit implements measures of protection, modification, or destruction of the critical data. For example, it may be provided, when an attack is detected, to interrupt the power supply of the chip or to cause its resetting, in order to reduce the time during which the attacker can study the chip response to a disturbance.
"Existing detection devices have various disadvantages. They for example require creating new structures in the chips to enable the detection of a laser attack. Further, they may increase the bulk and/or the complexity of secure devices."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "An embodiment provides a device for detecting a laser attack in an integrated circuit chip, which overcomes at least some of the disadvantages of the above-described devices.
"Thus, an embodiment provides a device for detecting a laser attack in an integrated circuit chip, formed in the upper P-type portion of a semiconductor substrate incorporating an NPN bipolar transistor having an N-type buried layer, comprising a detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate.
"According to an embodiment, the substrate comprises a substrate contact provided to be grounded, and the base contact of the NPN bipolar transistor is connected to a comparator and to a terminal of application of a bias voltage by a resistor.
"According to an embodiment, the collector and the base of the NPN bipolar transistor are interconnected.
"According to an embodiment, the resistor is embodied by a P-channel MOS transistor.
"According to an embodiment, the comparator comprises an inverter.
"According to an embodiment, the inverter comprises an N-channel MOS transistor and a P-channel MOS transistor, the gate width of the N-channel MOS transistor being at least twice smaller than that of the P-channel MOS transistor.
"The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a cross-section view schematically showing a portion of an integrated circuit chip;
"FIG. 2A is an electric diagram illustrating a device for detecting a laser attack; and
"FIG. 2B illustrates a variation of FIG. 2A.
"For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, FIG. 1 is not drawn to scale."
For additional information on this patent application, see: Marinet,
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