The patent's assignee for patent number 8508054 is
News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to bump pitches in flip-chip integrated circuit devices.
"Flip-chip integrated circuit (IC) devices include an IC die that is bonded to a substrate through one or more sets of solder bumps. The substrate facilitates interconnection between the IC die and a printed circuit board (PCB) on which the substrate is mounted. Through the PCB, the IC device can be coupled to a number of other devices mounted on the PCB.
"Lead-based solder bumps offer advantages in bonding an IC die to a substrate. For example, lead-based solder bumps are relatively flexible and have well-defined melting points. As such, lead-based solder bumps are well-suited to absorb stresses caused by coefficient of thermal expansion (CTE) mismatches between the IC die and the substrate.
"Nevertheless, lead-based solder bumps, like many lead-based products, have negative environmental effects. Thus, a trend has developed in which lead-based elements are removed from many products, including IC devices. This trend has resulted in a migration from lead-based solder bumps to lead-free solder bumps. These lead-free solder humps, however, are often not able to absorb stress caused by CTE mismatch, often resulting in the solder bumps cracking when the IC die and the substrate are bonded."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Methods and apparatuses for IC devices with enhanced bump pitches are provided. In an embodiment, an integrated circuit (IC) device is provided. The IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.
"In another embodiment, a method of assembling an integrated circuit (IC) device is provided. The method includes forming a first plurality of bond pads on a surface of an IC die, the surface of the IC die being configured to be bonded to a surface of an IC routing member and a pad of the first plurality of pads being offset relative to a respective pad of a second plurality of pads that are located on the surface of the IC routing member such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member and bonding the IC die onto the surface of the IC routing member."
For additional information on this patent, see: Pang, Mengzhi;
Keywords for this news article include:
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