The assignee for this patent, patent number 8508024, is
Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a chip packaging technology, and more particularly, to a package substrate and a chip package structure employing such the package substrate.
"Package substrates are a packaging component often used in current semiconductor packaging technology. The package substrate includes a plurality of patterned conductive layers and a plurality of dielectric layers alternatingly laminated with each other, and the adjacent layers can be electrically connected by the conductive vias. The two outmost patterned conductive layers respectively on the opposite surfaces of the package substrate include a plurality of pads. The package substrate further includes two solder-mask layers that cover the two outmost patterned conductive layers, respectively. These solder-mask layers have a plurality of openings. The openings expose portions of the pads, respectively, to define bonding areas of the pads.
"A chip may be assembled onto the package substrate by flip-chip bonding or wire bonding to form a chip package structure. In addition, the package substrate may further be assembled to an external component (e.g. a printed circuit board) via solder balls disposed on the pads of the package substrate. However, when the bonding area of the pad is defined by the opening of the solder-mask layer, i.e. the pad is of a solder-mask-defined (SMD) type, the solder ball contacts only portion of the pad. Therefore, the solder ball may not be stably adhered onto the pad, thus degrading the reliability of the chip package structure. In addition, fabrication process needs to vary based on the structure requirements of different package substrates."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Accordingly, the present invention is directed to a package substrate having improved reliability.
"The present invention is also directed to a chip package structure which includes the above-mentioned package substrate thus having improved reliability.
"The present invention provides a chip package structure adapted to be disposed on a carrier. The chip package structure includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The laminated layer has a first surface and a second surface opposite to each other. The patterned conductive layer is disposed on the first surface of the laminated layer and includes at least one inner pad. The solder-mask layer is disposed on the first surface of the laminated layer and has at least one opening from which the inner pad is exposed. The outer pad is disposed on the solder-mask layer and within the opening. The outer pad is connected with the inner pad exposed from the opening. The padding pattern is disposed on the solder-mask layer. A height of the padding pattern relative to the first surface of the laminated layer is greater than a height of the outer pad relative to the first surface of the laminated layer. The outer pad does not contact the carrier when the package substrate is disposed on the carrier with the padding pattern. The chip is disposed on the package substrate. The chip is located on the second surface of the laminated layer and electrically connected to the package substrate.
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