Researchers Submit Patent Application, "Semiconductor Device Capable of Adjusting Memory Page Size Based on a Row Address and a Bank Address", for Approval
The patent's assignee for patent application serial number 828604 is
News editors obtained the following quote from the background information supplied by the inventors: "Embodiments of the present inventive concept relate to a semiconductor device, and more particularly, to a semiconductor device capable of adjusting a page size, a multi-chip package including the semiconductor device, and a semiconductor system including the multi-chip package.
"Semiconductor memory is a semiconductor device, which may be used as computer memory. Examples of semiconductor memory include non-volatile memory such as Read-only memory (ROM), magnetoresistive random access memory (MRAM), flash memory, etc.
"Semiconductor memory may be divided into pages of a fixed size (e.g., 1K byte pages, 2k byte pages, etc). Data from each page can be accessed by using a binary address. For example, a 1K page has 2.sup.10 bytes, and thus data of the 1K page could be accessed using a 10 bit address. However, it may not be efficient to use a fixed page size. For example, if data is extracted from the memory in units of pages, the entire page needs to be accessed even though only a small portion of each page currently has data.
"Thus, there is a need for a semiconductor device that is capable of adjusting a page size, a multi-chip package including the semiconductor device, and a semiconductor system including the multi-chip package."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "A semiconductor device according to an exemplary embodiment of the inventive concept includes a memory cell array having a plurality of banks and a page size controller configured to decode a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable at two of the plurality of banks to set a page size of the semiconductor device.
"A semiconductor device according to an exemplary embodiment of the inventive concept includes a memory cell array having a plurality of banks and a page size controller configured to use a part of a row address as a chip ID and enable one bank among the plurality of banks based on a bank selection address in a first mode and to use a combination of a part of the bank selection address and the part of the row address as the chip ID and enable at least two banks among the plurality of banks based on a remaining part of the bank selection address in a second operation mode.
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