The patent's assignee for patent application serial number 364976 is
News editors obtained the following quote from the background information supplied by the inventors: "It is very common in the semiconductor (SC) device and integrated circuit (IC) arts to place contacts to a semiconductor (SC) body or layer in close proximity to other device regions that must remain substantially insulated from such contacts. A well known example is source and/or drain (S-D) contacts of field effect transistors (FETs).
"There is an ongoing need to provide ever denser and more complex SC devices and ICs. This is accomplished in part by reducing the dimensions and spacing of the various device regions. The spacing and alignment of the various device regions are generally determined lithographically, that is by using doping, deposition and/or etching masks. However, as dimensions of the various mask openings and the spacing of such openings become smaller and smaller, alignment tolerance and other errors inherent in the photo-lithographic process become more and more significant and can adversely affect manufacturing yield and cost. Thus, there is an ongoing need to provide contacts closely spaced to but insulated from other device regions or elements where the structure and process used to form such contacts are more tolerant of inherent errors in contact alignment, placement and/or size. This is especially important in connection with field effect transistors (FETs) but also applies to many other semiconductor devices and ICs where contacts must be placed in close proximity to but insulated from other electrical conductors or device regions. Accordingly, the present invention is not limited to FETs but applies generally to any type of semiconductor devices and ICs where such closely spaced contacts are needed."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "An integrated circuit with an alignment tolerant electrical contact (44) is formed by providing a substrate (21) with a first electrically conductive region (26) (e.g., a MOSFET gate) having an upper surface (262), wherein the electrically conductive region is laterally bounded by a first dielectric region (34), applying a mask having an opening (301) extending partly over a contact region (221) of the substrate (21) (e.g., for the MOSFET source or drain (22)) and over a part (263) of the upper surface (262), forming a passage (342) through the first dielectric region (34) extending to the contact region (221) and the part (263) of the upper surface (262), thereby exposing the contact region (221) and the part (263) of the upper surface (262), converting the part (263) of the upper surface (262) to a second dielectric region (264) and filling the passage (342) with a conductor (44) making electrical contact with the contact region (221) but electrically insulated from the electrically conductive region (26) by the second dielectric region (264).
BRIEF DESCRIPTION OF THE DRAWINGS
"The invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying figures in the drawings in which like numerals denote like or analogous elements, and wherein:
"FIGS. 1-4 show simplified cross-sectional views of a semiconductor device or portion of an integrated circuit (IC) embodying a FET whose source or drain contact is intended to be located in close proximity to but insulated from an adjacent conductive gate, illustrating how contact mis-alignment or mis-placement can result in an unintended short between the contact and the gate of the FET; and
"FIGS. 5-14 show simplified cross-sectional views of a semiconductor device or portion of an IC embodying a FET analogous to that of FIGS. 1-4 at various manufacturing stages and with the same contact mis-alignment or mis-placement shown in FIG. 3, but where the contact-gate short illustrated in FIG. 4 is avoided, according to an embodiment of the invention."
For additional information on this patent application, see: Labonte,
Keywords for this news article include: Electronics, Semiconductor,
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