No assignee for patent application serial number 725691 has been made.
News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to spectrographic monitoring of a substrate during chemical mechanical polishing.
"An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive, or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface and planarizing the filler layer. For certain applications, the filler layer is planarized until the top surface of a patterned layer is exposed. A conductive filler layer, for example, can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs, and lines that provide conductive paths between thin film circuits on the substrate. For other applications, such as oxide polishing, the filler layer is planarized until a predetermined thickness is left over the non planar surface. In addition, planarization of the substrate surface is usually required for photolithography.
"Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is typically placed against a rotating polishing disk pad or belt pad. The polishing pad can be either a standard pad or a fixed abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing liquid, such as a slurry with abrasive particles, is typically supplied to the surface of the polishing pad.
"One problem in CMP is using an appropriate polishing rate to achieve a desirable wafer profile, e.g., a wafer that includes a substrate layer that has been planarized to a desired flatness or thickness, or a desired amount of material has been removed. Overpolishing (removing too much) of a conductive layer or film leads to increased circuit resistance. On the other hand, underpolishing (removing too little) of a conductive layer leads to electrical shorting. Variations in the initial thickness of the substrate layer, the slurry composition, the polishing pad condition, the relative speed between the polishing pad and the substrate, and the load on the substrate can cause variations in the material removal rate. More generally, an actual polishing rate can be different from an expected polishing rate. Therefore, the polishing endpoint cannot be determined merely as a function of the polishing time."
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