The patent's assignee for patent number 8507970 is
News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure herein relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device.
"There continues to be an ever-increasing demand for further integration of semiconductor devices having superior performance and lower price. In semiconductor memory devices, a higher integration degree is particularly necessary, since the integration degree is a significant factor in determining the resulting price. In present two-dimensional or planar memory semiconductor devices, since the integration degree is determined by the occupying area of a unit memory cell, the integration degree is considerably affected by the technique for forming fine patterns. In order to achieve the formation of minute patterns, however, highly expensive equipment is necessary.
"As an alternative, development continues on techniques for forming three-dimensionally memory cells. According to these techniques, since memory cells are arranged in three-dimensions, the area of semiconductor substrate is effectively utilized. As a result, the integration degree may be largely increased as compared to the known two-dimensional memory semiconductor devices. In addition, word lines can be formed by using a patterning process to define an active region, thereby greatly reducing a manufacturing cost per unit bit of memory."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "The present disclosure provides a three-dimensional semiconductor memory device that offers reduced cost of manufacture and improved reliability.
"Embodiments of the inventive concept provide a three-dimensional semiconductor memory device including a semiconductor substrate having a recessed region; an active pattern extending in a direction transverse to the recessed region; an insulating pillar being adjacent to the active pattern and extending in the direction transverse to the recessed region; and a lower select gate facing the active pattern and extending horizontally on the semiconductor substrate, wherein the active pattern is disposed between the insulating pillar and the lower select gate.
"In some embodiments, the active pattern may have a cylindrical shape.
"In other embodiments, the active pattern may be disposed to cover a lower surface and a side surface of the recessed region, and wherein the insulating pillar may fill the recessed region in which the active pattern is disposed.
"In other embodiments, the position of a lower surface of the insulating pillar may be lower than that of an upper surface of the semiconductor substrate.
"In other embodiments, the three-dimensional semiconductor memory device may further include a common source lines present in the semiconductor substrate and extending in parallel along a direction in which the lower select gate extends.
"In other embodiments, the lower select gate may control a first channel region, which is defined in the semiconductor substrate between the active pattern and the common source line, and a second channel region, which is defined in the active pattern.
"In other embodiments, the first channel region may contain dopants which adjust a threshold voltage.
"In other embodiments, the first channel region may contain a first conductive type dopant, and the common source line may contain a second conductive type dopant.
"In other embodiments, the three-dimensional semiconductor memory device may further include: word lines and an upper select gate being disposed on the lower select gate so as to be spaced apart from each other and extending horizontally; and information storage layers interposed between the active pattern and the lower select gate, between the active pattern and the word lines, and between the active pattern and the upper select line.
"In other embodiments, the three-dimensional semiconductor memory device may further include a p-well provided in the semiconductor substrate, and the p-well may come into contact with the active pattern."
For additional information on this patent, see: Jeong, Jaehun; Kim, Hansoo; Jang, Jaehoon; Shim, Sunil. Three-Dimensional Semiconductor Memory Device. U.S. Patent Number 8507970, filed
Keywords for this news article include: Semiconductor,
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