Patent Issued for Semiconductor Devices Having Bit Line Interconnections with Increased Width and Reduced Distance from Corresponding Bit Line Contacts and Methods of Fabricating Such Devices
The patent's assignee for patent number 8507980 is
News editors obtained the following quote from the background information supplied by the inventors: "Embodiments of the inventive concept relate to semiconductor devices that include bit lines having a tab-structure and methods of fabricating such devices.
"As the integration density of semiconductor devices increases, the horizontal interval between adjacent metal interconnections that are formed in the same plane is reduced. The reduction in this horizontal interval between the adjacent metal interconnections may lead to an increase in parasitic capacitance between metal interconnections that are electrically isolated from each other by, for example, an insulating layer."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Embodiments of the inventive concept provide semiconductor devices in which a bit line interconnection that forms a contact with a drain region may have a greater width than a bit line interconnection that does not form a contact with the drain region, and methods of fabricating such semiconductor devices.
"Also, embodiments of the inventive concept provide semiconductor devices in which a bit line interconnection that forms a contact with a drain region may be at a lower level than a bit line interconnection that does not form a contact with the drain region.
"The technical objectives of the inventive disclosure are not limited to the above; other objectives may become apparent to those of ordinary skill in the art based on the following descriptions.
"In accordance with an aspect of the inventive concept, a method of fabricating a semiconductor device includes forming an isolation region in a substrate to define an active region. A buried gate electrode is formed that intersects the active region. Source and drain regions are formed in the active region. A first conductive pattern is formed on a top surface of the substrate. The first conductive pattern has a first conductive layer hole that exposes the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region such that a top surface of the second conductive pattern is closer to a bottom surface of the substrate than is a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures. Also, the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures.
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