Patent number 8508263 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to the control of a power-down mode of a semiconductor device.
"Semiconductor devices operating in synchronization with a clock include a clock supply circuit that generates an internal clock, which is to be used in the semiconductor devices, by using an external clock supplied from the outside of the semiconductor devices. Such a clock supply circuit may include a delay locked loop (DLL), a phase locked loop (PLL) and the like. The delay locked loop or the phase locked loop may supply a normal internal clock after a delay-locking or a phase-locking is completed.
"Meanwhile, the semiconductor devices may have a power-down mode in order to reduce the amount of current consumed, because, the semiconductor devices may have a period where no operation is performed. For example, a memory device may enter a power-down mode during the period when no data is inputted and outputted, where it does not perform operations on memory blocks except for a specific internal block.
"However, entering the power-down mode may be limited during a period for delay-locking or phase-locking of the internal clock. If the semiconductor devices enter the power-down mode, a delay-locking or phase-locking information is necessary for a normal operation to be performed after the semiconductor devices are switched from the power-down mode to a normal mode.
"If the semiconductor devices enter the power-down mode during the period the clock supply circuit is not locked, the clock supply circuit does not have locking information, and thus the semiconductor devices may not perform a normal operation after they are switched from the power-down mode to the normal mode. For this reason, the semiconductor devices using the clock supply circuit have a limitation in entering the power-down mode until the clock supply circuit is locked.
"FIGS. 1A and 1B are diagrams illustrating the period when an entry into a power-down mode is acceptable and the period when the entry into the power-down mode is unacceptable in a known memory device.
"Referring to FIG. 1A, during an initial operation of the memory device, a delay locked loop is turned on (DLL on) and is reset by mode register setting (MRS) (DLL reset), so that the delay locked loop starts an operation for locking. However, it is defined that the entry into the power-down mode is unacceptable during the time 101 (tDLL
"Meanwhile, it is defined that the entry into the power-down mode is acceptable after the time point 102 at which the locking of the delay locked loop has been completed. Accordingly, a memory controller gives a command for the entry into the power-down mode to the memory device after the time point 102.
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