The assignee for this patent, patent number 8508275, is
Reporters obtained the following quote from the background information supplied by the inventors: "In modern electronics, a flip-flop is a circuit that has two stable states and can be utilized to store state information, typically referred to as a '0' state or a '1' state that form the basic language of all modern computing systems. The flip-flop circuits are combined within the design of the computing system to store and process these states during operation of the computing system. Several different types of flip-flops exist in the art and are used in computing systems; including static flip-flops (providing a fixed static logic signal at the output) and dynamic flip-flops (providing a monotonic output if the input data is a logic '1' and a fixed '0' output if the data is '0'). In general, flip-flop circuits are the fundamental building blocks of digital electronic systems used in almost every modern computing device.
"In computing systems that incorporate a high-performance microprocessor, flip-flops are typically designed to provide short latency and the capability to incorporate logic functions with a minimum delay time penalty. One such design, known as the semi-dynamic flip-flop, comprises a dynamic front-end such that the flip-flop can operate on the clock signal of the system and a static back-end to hold the state of the flip-flop stable for use by the system during system operation. However, while known semi-dynamic flip-flops provide several advantages over previously designed flip-flops, there is always the need in high-performing computing systems for faster performing and more stable flip-flops. In addition, as computing devices become smaller and smaller, the space consumed within a microprocessor chip by any component of the microprocessor becomes important. In general, circuit design of a microprocessor balances the need for faster performance, area consumed and stability or reliability of the circuit.
"It is with these and other issues in mind that various aspects of the present disclosure were developed."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay. A PMOS keeper control device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS keeper control device and control signal effectively controls the high or logical '1' aspect of the keeper circuit by cutting off a PMOS transistor of the keeper circuit when the control signal is high and, after a three gate delay following the clock signal going high, energizing the PMOS transistor to sustain the precharge state of the dynamic node. The effective turning on and off of the PMOS transistor of the keeper circuit of the semi-dynamic flip-flop circuit removes the fight between the discharge of a dynamic node and the keeper circuit to increase the data to output delay of the flip-flop, resulting in higher performing microprocessors.
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