The assignee for this patent, patent number 8510521, is
Reporters obtained the following quote from the background information supplied by the inventors: "This invention is related to the field of memory controllers.
"Digital systems generally include a memory system formed from semiconductor memory devices such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM including low power versions (LPDDR, LPDDR2, etc.) SDRAM, etc. The memory system is volatile, retaining data when powered on but not when powered off, but also provides low latency access as compared to nonvolatile memories such as Flash memory, magnetic storage devices such as disk drives, or optical storage devices such a compact disk (CD), digital video disk (DVD), and BluRay drives.
"The memory devices forming the memory system have a low level interface to read and write the memory according to memory device-specific protocols. The sources that generate memory operations typically communicate via a higher level interface such as a bus, a point-to-point packet interface, etc. The sources can be processors, peripheral devices such as input/output (I/O) devices, audio and video devices, etc. Generally, the memory operations include read memory operations to transfer data from the memory to the device and write memory operations to transfer data from the source to the memory. Read memory operations may be more succinctly referred to herein as read operations or reads, and similarly write memory operations may be more succinctly referred to herein as write operations or writes.
"Accordingly, a memory controller is typically included to receive the memory operations from the higher level interface and to control the memory devices to perform the received operations. The memory controller generally also includes queues to capture the memory operations, and can include circuitry to improve performance. For example, some memory controllers schedule read memory operations ahead of earlier write memory operations that affect different addresses.
"Memory controllers have limited visibility to the different types of traffic that can be issued by the sources. Accordingly, memory controllers have not been able to segregate traffic at finer levels of granularity. Thus, performance improvements in memory controllers have been limited to the coarser mechanisms such as scheduling read operations prior to write operations."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In an embodiment, a memory controller includes several levels of reordering of memory operations between a plurality of ports on which the memory operations are received. The memory operations are received on the plurality of ports with corresponding quality of service (QoS) parameters. Reordering in the memory controller may be based initially on the QoS parameters. At lower levels of reordering, as the memory operations near the memory interface, factors that impact memory efficiency become more important in the reordering decisions and the QoS parameters become less important. Overall performance may be enhanced by considering both QoS parameters and memory efficiency in several levels of reordering."
For more information, see this patent: Biswas, Sukalpa; Chen, Hao. Reordering in the Memory Controller. U.S. Patent Number 8510521, filed
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