The assignee for this patent, patent number 8507981, is
Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a metal-oxide-semiconductor (MOS) transistor, especially referred to an n-type metal-oxide-semiconductor (NMOS) transistor and the manufacturing method thereof.
"MOS transistors are among most commonly used semiconductor components. MOS transistors include vertical double-diffused MOS (VDMOS) and laterally-diffused MOS (LDMOS). Because LDNMOS transistors have higher operation bandwidth, higher operation efficiency, and a flat structure that can be easily integrated with other integrated circuits, LDNMOS transistors are widely used in high voltage environment, such as in a CPU power supply, power management system, AC/DC converter and high power or high frequency power amplifier. The operation characteristics of LDNMOS transistors are similar to those of NMOS transistors. The difference between them is that the N-drift region of an NMOS transistor is highly doped while the N-drift region of an LDNMOS transistor is lowly doped. This makes the N-drift region of the LDNMOS bear most voltage drop between the drain and gate, reducing the high electric field between the drain and gate, and resulting in a high breakdown voltage of the LDNMOS transistor.
"Please refer to FIG. 1, FIG. 1 shows a prior art open drain circuit 100. As depicted in FIG. 1, an internal circuit 10 in the open drain circuit 100 is connected to an output driving element 11. The electro-discharge effect usually occurs at the input contact 15, output contact 16, high voltage contact 13 and low voltage contact 14. To prevent the output driving element 11 from electro-discharge damage, the ESD clamp 12 is added to protect the open drain element 11. Because the trigger voltage of the ESD clamp 12 is usually lower than that of the output driving element 11, the electro-discharge current will pass through the ESD clamp 12 rather than the output driving element 11.
"The ESD clamp 12 is usually made of NMOS transistors. The low trigger voltage of the NMOS transistor allows the NMOS transistor to discharge more quickly thereby demonstrating a high performance of the ESD clamp 12 to protect the open drain element 11. A typical approach to further improve the performance of the ESD clamp 12 is to reduce the channel length of the NMOS transistor so as to reduce the breakdown voltage of the NMOS transistor. However, reducing the channel length of the NMOS transistor will cause the NMOS transistor to leak current, reducing the reliability of the NMOS transistor."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "An embodiment of the present invention provides a method for forming an NMOS (n-type metal-oxide-semiconductor) comprising forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source comprising a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.
"Another embodiment of the present invention provides an NMOS (n-type metal-oxide-semiconductor) comprising a P-substrate; an N-well on the P-substrate; an N-drift region on the N-well; an n+ drain on the N-drift region; a plurality of first contacts on the n+ drain arranged along a longitudinal direction; a P-body on the N-well; a source on the P-body, the source comprising a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; a polygate on the P-body; and a gate oxide between the polygate and the source.
"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings."
For more information, see this patent: Chen, Lu-An; Lai, Tai-Hsiang; Tang, Tien-Hao. Method of Manufacturing NMOS Transistor with Low Trigger Voltage. U.S. Patent Number 8507981, filed
Keywords for this news article include: High Voltage, Semiconductor,
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