Patent number 8488400 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a semiconductor design technology, and more particularly, to a multi-port memory device for detecting a defect of a memory cell.
"Recently, the application range for a dynamic random access memory (DRAM) has been expanded from conventional devices such as desktop computers, laptop computers and servers to audio/video devices such as high definition television (HDTV). Accordingly, it is required that conventional way of data input/output of the DRAM be modified to a new way of data input/output. Herein, the conventional way of data input/output means a parallel input/output interface where a data exchange is performed through a single port which includes a plurality of input/output pins.
"FIG. 1 is a block diagram showing a conventional single-port memory device. In this particular example, the conventional single-port memory device is an x16, 512M DRAM which includes 8 banks.
"The conventional single-port memory device includes first to an eighth banks BANK0 to BANK7, a port (PORT), and a plurality of communication lines (GIO).
"Each of the first to the eighth banks BANK0 to BANK7 includes an n.times.m number of memory cells arranged in a matrix form. The port performs individual communication with the first to the eighth banks BANK0 to BANK7. The plurality of communication lines provides for a signal transfer between the port and a pin, and between the port and first to the eighth banks BANK0 to BANK7.
"Herein, the communication lines are global I/O lines generally included in the DRAM including a control bus, 15 lines of address bus and 16 lines of information bus.
"With conventional single-port memory devices, since a single-port is used, it is difficult to embody various multimedia functions. For embodying such multimedia functions using single-port memory devices, plural numbers of memory devices, e.g., DRAMs, should be independently constituted so that each DRAM performs a different function. However, in case of independently operating DRAMs, it is difficult to appropriately allocate memory among a plurality of devices which have different amounts of memory access. Therefore, memory usage efficiency is decreased compared with using a single memory device.
"For solving the above-mentioned problem, the applicant of the present invention proposed a multi-port memory device having a serial input/output interface as disclosed in a commonly owned copending application, U.S. Ser. No. 11/528,970, filed on
"FIG. 2 is a block diagram showing a conventional multi-port memory device.
"In the illustrated example, the multi-port memory device includes 4 ports, i.e., PORT0 to PORT3, 8 banks, i.e., BANK0 to BANK7, has a 16-bit data frame, and performs a 64-bit prefetch operation.
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