Patent number 8486794 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The disclosure relates in general to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure, comprising a step for forming a compensation layer.
"With a trend of shrinking a line width of a semiconductor process, a size of a semiconductor structure, comprising for example a MOS transistor or a memory array, etc., has been scaled down. However, an accurate process is necessary for obtaining a fine critical size of a semiconductor process. Otherwise, a semiconductor device would have a low efficiency resulted from a process shift or a side effect in a manufacturing step."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer is formed on a semiconductor substrate. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. A trench is formed in the compensation layer and the semiconductor substrate. An epitaxial layer is formed in the trench. The step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer.
"A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer and a cap layer are formed on a semiconductor substrate. The cap layer is on the patterned gate layer. A sidewall layer is formed on sidewalls of the patterned gate layer and the cap layer. The sidewall layer is removed. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. The cap layer is removed. The step for forming the compensation layer is between the step for removing the sidewall layer and the step for removing the cap layer.
"The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings."
URL and more information on this patent, see: Chou, Ling-Chun. Method for Manufacturing Semiconductor Structure. U.S. Patent Number 8486794, filed
Keywords for this news article include: Semiconductor,
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