Patent number 8610287 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "In the prior art, there is the wiring substrate which is applied as the semiconductor package for mounting the semiconductor chip. Such wiring substrate is manufactured based on laminating the wiring layers on the substrate by means of the build-up method.
"In Patent Literature 1 (Japanese Laid-open Patent Publication No. 2005-244108), it is set forth that, in the wiring substrate which has the pads in the openings of the dielectric layer on its surface, the wall surface conductor portion which is formed from the outer edge of the pad main body to the inner layer direction, along the wall of the opening portion, is provided on the back surface side of the pad, thereby the crack which is generated from the boundary between the pad and the dielectric layer as the starting point should be prevented.
"In Patent Literature 2 (Japanese Laid-open Patent Publication No. 2007-13092), it is set forth that the wiring substrate is obtained by forming to laminate the electrodes and the wiring portions connected thereto on the supporting substrate, and then removing the supporting substrate.
"As explained in the column of the related art described later, the connection pads (copper pad) of the wiring substrate on which the semiconductor chip is mounted are mounted on the mounting substrate via the solder bumps, and thus the electronic component module is constructed. In such electronic component module, particularly in the case that the wiring substrate is the coreless type, when the drop test is performed as a reliability test, a crack is easily generated from the periphery of the connection pad to the inner layer side. Therefore, such a problem arises that sufficient reliability cannot be obtained in use."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "According to one aspect discussed herein, there is provided a wiring substrate, which includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer, and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer arranged on the outer surface side, an intermediate metal layer arranged on a surface of an inner layer side of the first metal layer, and a second metal layer arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer.
"According to another aspect discussed herein, there is provided a method of manufacturing a wiring substrate, which includes forming a resist in which an opening portion is provided, on a supporting substrate, forming a metal laminated portion including a first metal layer, an intermediate metal layer, and a second metal layer in sequence from a bottom, in the opening portion of the resist by an electroplating, such that a hardness of the intermediate metal layer is set higher than hardness of the first metal layer and the second metal layer, removing the resist, forming an insulating layer in which the metal laminated portion is buried, on the supporting substrate, forming a wiring layer connected to the second metal layer via a via conductor provided in the insulating layer, on the insulating layer, and obtaining a connection pad including the first metal layer, the intermediate metal layer, and the second metal layer by removing the supporting substrate."
URL and more information on this patent, see: Kaneko, Kentaro; Kodani, Kotaro. Wiring Substrate and Method of Manufacturing the Same. U.S. Patent Number 8610287, filed
Keywords for this news article include: Electronics, Semiconductor,
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