Patent number 8609543 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a method for fabricating a semiconductor device, and more particularly, to an etching method employing a hard mask scheme in regions having different pattern densities.
"Large-scale integration trends have brought about a reduction of a critical dimension (CD) of a gate, and the reduction of the CD is required not only in a memory cell region but also in a peripheral region.
"A typical method for forming a gate in a semiconductor memory device employs a hard mask scheme to etch the gate. According to the hard mask scheme, there is formed a hard mask having substantially the same pattern as a photoresist pattern below the photoresist pattern to compensate limitations of the photoresist pattern that is independently used as an etch mask. Then, the photoresist pattern is removed and the hard mask is only used as an etch mask to the etch.
"In a process of forming the gate according to the typical method, a hard mask in the memory cell region is formed to have a thickness substantially the same as that in the peripheral region or each region has a stack structure of layers having substantially the same thickness as that in the other region.
"However, in the typical method, there is an increased etch rate in the peripheral region having a lower pattern density than the memory cell region because of a loading effect due to a difference of the pattern densities between the memory cell region and the peripheral region. Also, undue polymers are accumulated in the peripheral region compared to the memory cell region. Accordingly, a slope generated during the gate etch process in the peripheral region is steeper than that in the memory cell region and, thus, the reduction of the CD of the gate in the memory cell is less than that in the peripheral region. As a result, a difference of the CDs between the memory cell region and the peripheral region increases."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Embodiments of the present invention are directed to provide a method for fabricating a semiconductor device. The method prevents an increase of a gate CD difference between a memory cell region having a high pattern density and a peripheral region having a low pattern density.
"In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor device. The method includes providing a substrate having a first and a second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer to have different thicknesses over the first and the second regions, forming a hard mask pattern by etching the hard mask layer, and etching the etch target layer using the hard mask pattern as an etch mask to form a target pattern having different densities over the first and the second regions."
URL and more information on this patent, see: Kim, Myung-Ok; Jung, Tae-Woo. Method for Manufacturing Semiconductor Device Having Multi-Layered Hard Mask Layer. U.S. Patent Number 8609543, filed
Keywords for this news article include: Electronics,
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