Patent number 8609530 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a method for forming a three-dimensional metal-insulator-metal capacitive structure in an interconnection stack, and to the resulting structure.
"Conventionally, to provide integrated circuit chips, electronic components are formed at the surface of a semiconductor substrate. To connect the electronic components to one another, a stack of interconnection levels comprising metal tracks and vias surrounded with a dielectric material is formed above the substrate. Each level of the interconnection stack conventionally comprises a first stage in which are formed metal vias (called 'via level' hereafter) and a second stage in which are formed metal tracks (called 'metal level' hereafter).
"The direct integration of capacitive metal-insulator-metal structures (better known as MIMs) in certain portions of the interconnection levels is known. FIG. 1 illustrates an example of such a structure as described, for example, in 'High performance 3D damascene MIM capacitors integrated in copper back-end technologies' by S.
"FIG. 1 partially shows three interconnection levels L.sub.n-1, L.sub.n, and L.sub.n+1, each level comprising a via level, respectively V.sub.n-1, V.sub.n, and V.sub.n+1, and a metal level, respectively M.sub.n-1, M.sub.n, and M.sub.n+1.
"Metal tracks 10 are formed in each of metal levels M.sub.n-1, M.sub.n, and M.sub.n+1. Metal tracks 10 are, for example, made of copper or of aluminum. In each of via levels V.sub.n-1, V.sub.n, and V.sub.n+1 are provided conductive vias 12 enabling to connect metal tracks 10 of adjacent interconnection levels to one another. A dielectric material 14 surrounds the conductive regions of the interconnection stack and insulates these regions from one another. An insulating layer 16 is provided at the surface of each of metal levels M.sub.n-1, M.sub.n, and M.sub.n+1 and of via levels V.sub.n-1, V.sub.n, and V.sub.n+1. Layer 16, generally made to of silicon nitride, aims at avoiding the diffusion of the metal from a metal or via level to adjacent levels.
"In the example of FIG. 1, a capacitive structure C.sub.V is provided in via level V.sub.n. Capacitive structure C.sub.V is formed above a metal track 10 of metal level M.sub.n-1, in a trench made in dielectric material 14 of via level V.sub.n. Capacitive structure C.sub.V comprises a first conductive layer 18 forming a first electrode which extends on the walls and the bottom of the trench, in contact with track 10. At the surface of first electrode 18 is formed a stack of a layer of a dielectric material 20 and of a second conductive layer 22 forming the second electrode of the capacitive structure. The rest of the trench is filled with a conductive material.
"To take a contact on first electrode 18, vias are provided in via level V.sub.n above metal track 10 of metal level M.sub.n-1. To form a contact with second electrode 22, a metal track portion is provided, in metal level M.sub.n, above conductive region 24. A via is provided in via level V.sub.n+1, above this track portion.
"To obtain the structure of FIG. 1, additional steps with respect to conventional methods for forming an interconnection stack are necessary. Indeed, capacitive structure C.sub.V is formed in via level V.sub.n before forming metal level M.sub.n and the tracks and vias of interconnection level L.sub.n. Further, in a structure such as that in FIG. 1, the series resistance associated with the capacitor is large and limits the high-frequency performance of the component.
"Indeed, capacitor C.sub.V is formed by the placing in parallel of a 'horizontal' capacitor, in the bottom of the trench formed in via level V.sub.n, and of a 'vertical' capacitor, formed at the level of the trench walls. The small thickness of conductive layer 18 implies a significant access resistance at the level of the walls of the capacitive structure, which limits cut-off frequency Fc of the component, defining the limit of the use of the component as a capacitor (as a first approximation, Fc=.pi.*R*C/2, where R is the series resistance of the component and C its capacitance).
"The component is thus only advantageous at low frequency.
"Further, in a structure such as that in FIG. 1, metallization M.sub.n cannot be used above capacitive structure C.sub.V. Indeed, to avoid forming short-circuits, the metal tracks located above conductive region 24 can only actually play the role of access vias and cannot be directly connected to other tracks of the same level. Thus, the surface above the capacitive structure cannot be used to form other conductive tracks. Two interconnection levels L.sub.n and L.sub.n-1 are thus necessary to form capacitive structure C.sub.V.
"The forming of three-dimensional capacitive structures such as capacitive structure C.sub.V over the entire thickness of an interconnection level is also known. However, to obtain such a structure, relatively complex methods may be needed.
"There thus is a need for a method for forming capacitive metal-insulator-metal structures in the interconnection stack of an integrated circuit, which overcomes all or part of the above-mentioned disadvantages."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An object of an embodiment of the present invention is to provide a relatively simple method for forming a three-dimensional capacitive metal-insulator-metal structure in a level of an interconnect stack.
"Another object of the present invention is to provide a method for forming a three-dimensional capacitive metal-insulator-metal structure in an interconnection stack, which takes up a limited surface area of this stack.
"An object of the present invention more generally is to provide a three-dimensional capacitive metal-insulator-metal structure formed in a single metal level of an interconnect stack, this capacitive structure having a significant capacitance per surface area unit.
"Thus, an embodiment of the present invention provides a method for forming a capacitive structure in a metal level of an interconnection stack comprising a succession of metal levels and of via levels, comprising the steps of:
"(a) forming, in said metal level, at least one conductive track in which a trench is defined;
"(b) conformally forming an insulating layer on the structure;
"© forming, in the trench, a conductive material; and
"(d) planarizing the structure.
"According to an embodiment of the present invention, step (b) is preceded by a step of forming a conformal conductive layer.
"According to an embodiment of the present invention, step (a) comprises forming a conductive track in the metal level and then performing a reactive ion etching of the conductive track to form a through trench.
"According to an embodiment of the present invention, the forming of the conductive track comprises an intermediary step of forming of a conductive layer forming a barrier in the conductive track, the etching of the conductive track being selective over said conductive barrier-forming layer.
"According to an embodiment of the present invention, step (a) comprises forming portions of conductive tracks surrounding an insulating region and then selectively etching the insulating region.
"According to an embodiment of the present invention, the method further comprises, after step (d), a step of forming of a layer forming a barrier against the diffusion of the material of the conductive track.
"According to an embodiment of the present invention, the trench has, in top view, a comb shape.
"According to an embodiment of the present invention, the method further comprises, after step (b), a step of forming of a conformal conductive layer.
"According to an embodiment of the present invention, the method further comprises, after step (d), a step of forming of a via level on the metal level in which a conductive via is provided in front of the conductive material.
"An embodiment of the present invention provides an electronic device comprising a stack of interconnection levels, each interconnection level comprising a via level topped with a metal level, further comprising, in at least one metal level, at least one conductive track in which is defined at least one trench, a three-dimensional capacitive element being formed in the trench, said capacitive element comprising at least one insulating layer formed on the bottom and the walls of the trench, the trench being filled with a conductive material.
"The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings."
URL and more information on this patent, see: Jeannot, Simon; Tannhof, Pascal. Method for Forming a Three-Dimensional Structure of Metal-Insulator-Metal Type. U.S. Patent Number 8609530, filed
Keywords for this news article include: Electronic Components,
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