Patent number 8612661 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Embodiments described herein relate to an interrupt-notification control unit and a semiconductor integrated circuit, and methods therefor.
"A technology called interrupt coalescing is well known in computer systems.
"Generally, interrupt coalescing may be applied to an interrupt-notification control unit (interrupt controller) that connects an interrupt dispatcher that issues an interrupt request and a processor having an interrupt input terminal.
"The basic concept of the interrupt coalescing is to prevent an increase in load on the processor due to a high frequency of interrupts.
"The interrupt coalescing reduces overhead of the processor associated with interrupt handling, such as starting/stopping an interrupt handler, by delaying the time of sending an interrupt request to the processor under fixed conditions and sending the request to the processor together with a plurality of interrupt requests issued later.
"FIG. 1 is a schematic block diagram of an example of a typical interrupt-notification control unit, schematically representing an interrupt controller incorporating basic interrupt coalescing. FIG. 2 is a conceptual block diagram of a delay control unit in the interrupt-notification control unit in FIG. 1.
"In FIG. 1, the reference numeral 501 denotes an interrupt controller (interrupt-notification control unit), 502 denotes a processor, and 503 denotes an interrupt dispatcher. In FIG. 2, reference numeral 511a denotes a delay limit counter, and 511b denotes an AND gate.
"As illustrated in FIG. 1, the interrupt controller 501 includes a delay control unit 511 and a condition register 512.
"Assume that, in the interrupt controller 501 illustrated in FIG. 1, a condition (interrupt delay condition) in the condition register 512 is 'delay a notification until X interrupt requests are issued'.
"At that time, the number of times 'X' is held in the condition register 512. When the delay limit counter 511a in the delay control unit 511 counts X times of interrupt notification (interrupt request) IR from the interrupt dispatcher 503, a high level '1' is output to the AND gate 511b.
"Thus, the AND gate 511b sends the X times of previous interrupt request IR to the processor 502 at the time of high level '1' due to the X-th interrupt request.
"FIG. 2 illustrates the concept of the delay control unit 511, in which a latch circuit or the like for holding X times of interrupt request IR from the interrupt dispatcher 503 is practically provided.
"Specifically, the delay control unit 511 delays interrupt notification to the processor 502 during the time after the first interrupt request
"The use of this method may substantially reduce the number of times of interrupt to processor 502 to 1/X, thereby reducing overhead associated with interrupt handling.
"Various modifications of interrupt coalescing have been proposed in the related art; Japanese Laid-open Patent Publication Nos. 2008-217821 and 2002-182930 describe typical methods for delaying the time at which a plurality of interrupt requests are sent."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "According to an aspect of the embodiment, an interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the interrupt-notification control unit determines a correlation among the interrupt requests to control time to send the interrupt requests together to the processor.
"An embodiment is directed to a method of controlling an interrupt request including determining a correlation among interrupt requests to control a time to send the interrupt requests collectively to a processor.
"The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
"It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. Additional aspects and/or advantages will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the invention."
URL and more information on this patent, see: Shimada, Takashi.
Keywords for this news article include: Electronics,
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