Patent number 8607022 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "This disclosure is related to the field of computer systems, and more particularly to systems and methods for processing quality-of-service (QoS) information of memory transactions.
"Some computers feature memory access mechanisms that allow hardware subsystems or input/output (I/O) peripherals to access system memory without direct interference from a central processing unit (CPU) or processor. As a result, memory transactions or requests involving these peripherals may take place while the processor continues to perform other tasks, thus increasing overall system efficiency. Moreover, enabling a variety of circuits to access a common memory creates situations where the memory may have to make decisions as to the order in which received requests are processed, for example.
"To allow the memory to make these types of decisions, a quality-of-service (QoS) mechanism may be implemented such that an entity generating a memory request may also provide information representing the QoS associated with that request. In a typical scenario, every circuit in the path of a memory request or transaction containing QoS information must be capable of processing that information--or at least of forwarding the information to a subsequent circuit which is then capable of processing it."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "This specification discloses systems and methods for processing quality-of-service (QoS) information of memory transactions. As such, systems and methods disclosed herein may be applied in various environments, including, for example, in computing devices that provide peripheral components with access to one or more memories. In some embodiments, systems and methods disclosed herein may be implemented in a system-on-a-chip (SoC) or application-specific integrated circuit (ASIC) such that several hardware and software components may be integrated within a single circuit. Examples of electronic devices suitable for using these systems and methods include, but are not limited to, desktop computers, laptop computers, tablets, network appliances, mobile phones, personal digital assistants (PDAs), e-book readers, televisions, video game consoles, etc.
"In some embodiments, a system and method may include a logic circuit receiving identification information and QoS information corresponding to an original memory transaction transmitted from a hardware subsystem (e.g., a peripheral device, etc.) to a memory. This information may be received, for example, from a coherent interface circuit, or the like. In some embodiments, the interface circuit may extract the identification and QoS information from the memory transaction prior to forwarding it to a processor complex. In other embodiments, the interface may provide a copy of the memory transaction to the logic circuit so that the logic circuit may itself extract this information. Once obtained, the identification and QoS information may be stored, for example, in a buffer or the like.
"The interface circuit may provide the original memory transaction to a processor complex so that the processor complex may perform any number of operations including, for example, cache coherency operations or the like. In some cases, the processor complex may not support QoS encoding, and some or all QoS information may be altered and/or lost during its processing. Thus, if the processor complex cannot satisfy the original memory transaction with its cache, for example, the processor complex may then forward that transaction to the memory--but the forwarded memory transaction may no longer encode its original QoS information.
"Therefore, in some embodiments, upon exiting the processor complex and before reaching the memory, the forwarded memory transaction may be received by the logic circuit. The logic circuit may determine, based at least in part on previously stored identification information, whether this newly received memory transaction matches the original memory transaction. In response to the newly received memory transaction matching the original memory transaction, the logic circuit may then append the corresponding (and previously stored) QoS information to the newly received memory transaction before transmitting it to the memory.
"Accordingly, a logic circuit may effectively provide a bypass path that allows information (e.g., QoS information) to circumvent a circuit (e.g., a processor complex) that does not otherwise support (or properly processes) that type of information. Although described as QoS information in various implementations discussed herein, these techniques enable the bypassing of any other information (e.g., user-defined bits, etc.) around any type of circuit.
"In some embodiments, a system-on-chip (SoC) may include a memory, a processor complex coupled to the memory, an interface circuit coupled to the processor complex, and a logic circuit coupled to interface circuit, to the processor complex, and to the memory. The logic circuit may be configured to receive, from the interface circuit, identification information and user-defined information (e.g., QoS bits, etc.) corresponding to a first transaction. The logic circuit may also be configured to receive, from the processor complex, a second transaction that includes identification information but does not include user-defined information. Additionally or alternatively, the second transaction may include an altered version of its original user-defined information. The logic circuit may be further configured to determine that the second transaction matches the first transaction and insert the original user-defined information corresponding to the first transaction into the second transaction before transmitting the second transaction to the memory.
"In yet other embodiments, a logic circuit may include a first buffer configured to store QoS information corresponding to an original memory transaction and a second buffer configured to store a given memory transaction. The logic circuit may also include a QoS circuit coupled to the first and second buffer and that configured to determine whether the original memory transaction matches the given memory transaction based at least in part on a comparison between identification information of the original and given memory transactions. The QoS circuit may be further configured to add the stored QoS information to the given memory transaction in response to the given memory transaction matching the original memory transaction.
"In some embodiments, the memory transaction leaving the processor complex may not match the original transaction for which a logic circuit has stored QoS information. For example, the memory transaction may have been originated within the processor complex, and therefore its identification information may not match any identification information previously stored in the logic circuit. Further, if the processor complex does not support QoS encoding, then this transaction may not have QoS information. In those cases, the logic circuit may optionally generate QoS information based, for example, on the type of memory transaction--and it may insert the generated QoS information into the transaction before transmitting it to the memory."
URL and more information on this patent, see: Balkan, Deniz; Saund, Gurjeet S.; Gupta, Vijay. Processing Quality-Of-Service (QoS) Information of Memory Transactions. U.S. Patent Number 8607022, filed
Keywords for this news article include:
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