Patent number 8603893 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "As integrated circuits (ICs) become larger and larger it becomes necessary to consider structures other than planar transistors to accommodate the ever increasing number of transistors that the circuits require. One such structure is the FinFET, a field effect transistor (FET), in which the channel of the transistor is formed along the vertical sidewalls of a thin semiconductor fin that extends upwardly from a semiconductor substrate. Because the channel is formed along a vertical fin sidewall rather than along the horizontal surface of the wafer, a wide channel (and hence high performance) can be achieved without increasing the horizontal surface area of the semiconductor substrate.
"The fabrication of FinFET ICs, however, encounters some processing problems. Fin fabrication requires etching trenches into a semiconductor substrate to produce the vertical fins. The fins are usually formed in a wide array that extends across an entire IC chip. Among the problems encountered are the loading effects that arise when etching a plurality of fins. Larger open areas have a tendency to produce wide fins and deep trenches while more closely spaced fins are thin with much shallower trenches. Such variance in fin width and trench depth makes reliable processing difficult because the etch results become layout and thus product dependent. A common solution to the etch pattern loading problem is to include dummy fins to achieve a regular array in which all fins can be etched equally. If the FinFET is fabricated on a semiconductor-on-insulator (SOI) substrate, the removal of the dummy fins to achieve the necessary fin-fin electrical isolation is relatively easy. On bulk semiconductor wafers, however, such dummy fin removal and electrical isolation is not easy.
"Accordingly, it is desirable to provide methods for fabricating FinFET integrated circuits on bulk semiconductor substrates. In addition, it is desirable to provide methods for fabricating FinFET integrated circuits having the necessary electrical isolation between fins. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.
"In accordance with a further embodiment, a semiconductor substrate is provided and a patterned hard mask is formed overlying the semiconductor substrate, the patterned hard mask defining locations of a plurality of parallel fins extending in a first direction. A first etch mask exposing a first portion of the patterned hard mask is formed overlying a logic portion of the integrated circuit and a second portion of the patterned hard mask is formed overlying a memory portion of the integrated circuit, the first mask extending in a second direction including a portion substantially perpendicular to the first direction. Portions of the patterned hard mask are etched using the first etch mask to remove the first portion and the second portion. The semiconductor substrate is etched using remaining portions of the patterned hard mask as an etch mask to form a plurality of semiconductor fins separated by etched trenches. A second etch mask is formed overlying the plurality of semiconductor fins and portions of the plurality of semiconductor fins exposed through the second etch mask are etched to at least partially remove portions of the plurality of semiconductor fins. An insulator material is deposited to fill the trenches and to cover the etched portions of the plurality of semiconductor fins.
"In accordance with yet another embodiment, a semiconductor substrate is provided and a first mask is formed overlying the semiconductor substrate and defining a plurality of parallel fin locations extending in a first direction and selectively cut in a second direction. The semiconductor substrate is etched using the first mask as an etch mask to form a plurality of parallel fins extending in a first direction and separated by etched trenches, at least selected ones of the parallel fins being terminated in the second direction. A second mask is formed overlying the fins and exposing dummy ones of the plurality of parallel fins. At least a portion of the dummy ones of the plurality of parallel fins are etched to reduce the height thereof, and the trenches are filled and the etched dummy fins are covered with an insulating material."
URL and more information on this patent, see: Wei,
Keywords for this news article include: Electronics, Semiconductor,
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