Patent number 8605846 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "A. Technical Field
"The present invention relates to the field of electronics and data communication, and more particularly, to systems, devices and methods of employing an internal frequency synthesizer to generate high frequency oversampling clocks adaptive to predetermined parameters, such as a bit depth and an oversampling rate, for a serial data interface.
"B. Background of the Invention
"A large amount of signals are transmitted between different components in an embedded hardware system, and to maintain high efficiency, the signals have to be coordinated using a specific signal transmission standard. The Serial Peripheral Interface (SPI) is a generic standard applicable to most embedded systems. It is a synchronous serial data link standard which connects a master device and its slave devices through four standard logic signals, serial clock (SCLK), data in (DIN), data out (DO) and slave select (SS). Input serial data are synchronized with the input serial clock and converted to parallel control outputs in the slave devices under the control of the slave select. The data are returned from the selected slave device as a serial digital signal or as an analog signal, and thus, only one output pin is needed for the master device to receive the outcome. As the parallel-to-serial and serial-to-parallel data shifting techniques mature, the use of the Serial Peripheral Interface allows tremendous pin count reduction and board real estate saving while consuming only limited chip area for data shifting. Nowadays, the Serial Peripheral Interfaces are used in microprocessors, microcontrollers and their peripherals such as sensors, actuators, cameras, memory arrays and displays.
"In many digital audio systems, the Serial Peripheral Interface may be further simplified to a three-signal Integrated Interchip Sound (I2S) interface. These audio systems normally include audio media (tape, compact disc or digital TV sound) and a number of processing circuits comprising analog-to-digital converters (ADCs), digital-to-analog converters (DACs), error correction circuit, digital filters and interface electronics. The data out signal in the SPI is also needed in the I2S interface when returned data are involved in some audio applications, such as audio ADCs. The slave select signal in the SPI is converted to a low frequency left/right clock (LRCLK), which is also called as word select (WS). In a stereo system, the left/right clock multiplexes two audio channels through its logic levels in the time domain. The audio information is stored in the data in (DIN) signal and the DIN signal is synchronized with the serial clock (SCLK) which is often called as bit clock (BCLK) in audio applications. Most audio systems function under the control of such a three- or four-signal I2S interface comprising the bit clock, the left/right clock and the serial data in and/or serial data out.
"The SPI interface and the I2S interface meet data communication requirements in most embedded and audio systems; however, additional high frequency clock signals may be required in some applications. For example, A/D and D/A converters in many audio systems involve sigma-delta (.SIGMA.-.DELTA.) modulation and a high frequency master clock (MCLK) is required for oversampling in A/D or D/A conversion. The frequency of the master clock is an integer multiple, typically 128, of the left/right clock frequency. This ratio of the MCLK/LRCLK is also referred to as the oversampling rate. The master clock is used to generate an oversampling clock, and therefore, the jitter noise of the master clock has to be low enough to avoid degrading the audio quality. Constrained by such a low jitter requirement, the A/D and D/A converters in prior arts rely on external master clock signals. However, the incoming master clock is required to synchronize with the I2S interface, and the drive circuit of the master clock may dominate power consumption in the input/output (I/O) interface and potentially causes electromagnetic interferences or compatibility (EMI/
"Data transmission using serial data interfaces has significantly reduced the pin count for integrated circuit components. However, additional pin count reduction is highly desirable in order to further simply system integration and enhance cost efficiency. The prior arts in some audio applications reduce the pin count by regenerating the bit clock from the master clock using digital dividers. The aforementioned issue of power consumption still exists. Data clock synchronization becomes another challenge and may impose unexpected constraints on clock timing."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Various embodiments of the present invention relate to systems, devices and methods of frequency synthesis that generate a higher frequency oversampling clock signal adaptive to predetermined parameters. This adaptive frequency synthesis is monolithically integrated into integrated circuit (IC) components to reduce the pin count and improve cost efficiency.
"Certain embodiments of the IC components that adaptively synthesize the oversampling clock are the Integrated Interchip Sound (I2S) devices, such as an I2S digital-to-analog converter (DAC). The I2S DAC receives a bit clock, a left/right clock and input serial data from the I2S interface bus, and it comprises a frequency detector, a clock generator, a shift register and a DAC core. The frequency detector determines an output frequency control needed for the clock generator to generate the synchronous oversampling clock that can provide a desired oversampling rate for the input left/right clock. Although an I2S DAC normally has a limited number of combinations for the left/right clock and the bit clock frequencies, the clock frequencies are unknown to the I2S DAC upon receiving them. The bit depth is determined by the number of BCLK clock cycles that are counted in half of a left/right clock cycle. In one embodiment, a reference clock is needed to further identify the absolute magnitude of the clock frequencies from the available combinations. This reference clock frequency within a rough range of a known frequency is sufficient to instruct the frequency detector to generate the appropriate output frequency control. The clock generator is therefore controlled to generate an oversampling clock that is used for .SIGMA.-.DELTA. modulation in the DAC core. The frequency of the oversampling clock matches a desired oversampling rate which is usually 64-256 times of the left/right clock frequency.
"To further reduce the pin count of an I2S DAC, only one of the bit clock or the left/right clock is needed besides the input serial data from an I2S interface bus. The other clock is generated locally on chip. In one embodiment, the bit clock is the only input clock, and the left/right clock is generated by a digital divider according to the predefined bit depth while the rest of the I2S DAC remains the same for the oversampling clock generator and DAC core. In another embodiment, the left/right clock is the only input clock directly used for adaptive oversampling clock synthesis and the bit clock is obtained by dividing down the oversampling clock. The generated clocks, oversampling clock, bit clock or left/right clock, are adaptive to the predetermined bit depth and oversampling rate.
"One skilled in the art will recognize that the methods of generating the oversampling clock are applicable to any serial data system where a high frequency oversampling clock is needed. In one embodiment, a serial periphery interface (SPI) devices may use this method to generate oversampling clocks.
"Certain features and advantages of the present invention have been generally described in this summary section; however, additional features, advantages, and embodiments are presented herein or will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims hereof. Accordingly, it should be understood that the scope of the invention shall not be limited by the particular embodiments disclosed in this summary section."
URL and more information on this patent, see: Felder, Matthew; Summers, Mark. Adaptive Frequency Synthesis for a Serial Data Interface. U.S. Patent Number 8605846, filed
Keywords for this news article include: Electronics, Digital To Analog,
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