Bulk materials commonly used to make CMOS transitors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing "contact resistance" between them, both of which lead to degrading performance and rising energy consumption.
"In addition to its atomically thin and pristine surfaces, graphene has a tunable band gap, which can be adjusted by lithographic sketching of patterns - narrow graphene ribbons can be made semiconducting while wider ribbons are metallic. Hence, contiguous graphene ribbons can be envisioned from the same starting material to design both active and passive devices in a seamless fashion and lower interface/contact resistances," explained
"Accurate evaluation of electrical transport through the various graphene nanoribbon based devices and interconnects and across their interfaces was key to our successful circuit design and optimization," explained
"This work has demonstrated a solution for the serious contact resistance problem encounterd in conventional semiconductor technology by providing an innovative idea of using an all-graphene device-interconnect scheme. This will significantly simplify the IC fabrication process of graphene based nanoelectronic devices." commented
As reported in their study, the proposed all-graphene circuits have achieved 1.7X higher noise margins and 1-2 decades lower static power consumption over current CMOS technology. According to Banerjee, with the ongoing worldwide efforts in patterning and doping of graphene, such circuits can be realized in the near future.
"We hope that this work will encourage and inspire other researchers to explore graphene and beyond-graphene emerging 2-dimensional crystals for designing such 'band-gap engineered' circuits in the near future," added Banerjee.
Keywords for this news article include: Technology,
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