Patent number 8566647 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "A current focus for improving processor power is to provide multiple processor cores on a die to increase processor throughput. Central processing units, in higher-performing computing devices, such as workstations and servers, often include several processor cores included on a single die. Many of these devices also include one or more graphics processing units that each can include hundreds of processor cores on a single die. Graphics processor units, in addition to providing computations for computer graphics, are often configured to provide computations in applications previously provided by the central processing with a technique referred to as general purpose computing on graphics processing units, or GPGPU. In one example, GPGPU computing uses central processing units and graphics processor units together in a heterogeneous co-processing computing model. The sequential or relatively light-parallel parts of the application runs on the cores in the central processing units, and the computationally-intensive, often massively-parallel parts of the application are accelerated by the many cores in the graphics processing units. Parallel computer applications having many concurrent threads executed in GPGPU computing can realize a performance boost ten to one hundred times that over the applications executed on multiple core central processing units. Additionally, GPGPU systems typically are less expensive and use less power per core than multiple core central processing units.
"Parallel computer applications having concurrent threads and executed on multiple processors present great promise for increased performance but also present great challenges to developers. The process of developing parallel applications is challenging in that many common tools, techniques, programming languages, frameworks, and even the developers themselves, are adapted to create sequential programs."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
"The present disclosure describes user interface technologies for viewing the state of threads of a target parallel application, such as a massively parallel application intended to run on a GPGPU system, during debugging. The user interface technologies can also apply to target parallel applications in GPGPU software emulators, clusters or other device that executes programs having a large number of threads in parallel. A debugger is set to focus on a kernel of the target parallel application, and each kernel includes a plurality of thread groups each including a plurality of threads. When the target kernel enters break state, for example, the debugger has a notion of a current thread, and a current stack frame. The debugger determines a current thread group and information related to the threads. The thread information is collected and provided to a user interface and can be included within a presentation layer of the debugger. Coalesced thread information of the threads is presented based on user-controllable criteria. For example, coalesced thread information of the threads can be based by thread group vector, thread status, or source location, among other user-controllable criteria."
URL and more information on this patent, see: Maybee,
Keywords for this news article include: Technology,
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