Our news journalists obtained a quote from the research, "This implementation starts with a generic VHDL specification and then it is developed on FPGA architecture. The compression filter implementation on FPGA lets us eliminate special chips previously needed. The achieved design can be adapted to different computational requirements, easily modifying its data path and the length of the used signal sequence. From the experimental results it is known that this approach appears to work well for chirp and discrete phase matched/mismatched pulse compression and it outstands when TB is of order 1000. Also, it fits for arbitrary spread spectrum waveforms."
According to the news editors, the research concluded: "The design performances have been analyzed modifying the used precision and the length of the used signal sequences."
For more information on this research see: Hardware implementation of DIRLS mismatched compressor applied to a pulse-Doppler radar system. Microprocessors and Microsystems, 2013;37(4-5):381-393. Microprocessors and Microsystems can be contacted at: Elsevier Science Bv, PO Box 211, 1000 Ae
The news correspondents report that additional information may be obtained from S. Simic, Peripolis Elekt,
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