Patent number 8559576 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to circuits and techniques for synchronizing signals. More specifically, the present invention relates to circuits and techniques for adaptively synchronizing signals between different time domains.
"Clock signals are often distributed over an entire integrated circuit. However, as the clock frequencies and the number of transistors on an integrated circuit increases, it becomes increasingly difficult to implement such global clocks. Moreover, integrated circuits commonly contain different functional blocks that operate at different speeds. Consequently, many integrated circuits include multiple timing domains. In such integrated circuits, synchronizers are often used to interface the different timing domains.
"FIG. 1 shows an existing system 100 in which data 116 is communicated between timing domains 110 by transmitter 112 and receiver 114, and wherein synchronizers 118 are used to synchronize the different timing domains 110. When the transmitter 112 wants to transmit data to the receiver 114, it sends the data 116 and a request 124 signal, which is synchronized to the clock of receiver 114 (clk_receiver 126) before being read by the receiver 114. Once the receiver 114 has read the data 116, it sends an acknowledge 122 signal, which is synchronized to the clock of transmitter 112 (clk_transmitter 120). Unfortunately, this synchronization technique often suffers from a large latency because of the synchronization overhead in both the request and acknowledge paths.
"Furthermore, many synchronizers, such as synchronizers 118, have fixed configurations, such as synchronizers that include a fixed number of flip-flop stages. This can be problematic because a fixed synchronizer configuration can lead to problems with metastability, in which the output state of one or more flip-flops or the synchronizer becomes unpredictable. In particular, if data is clocked at a slow rate, i.e., if there is enough settling time, synchronizers that have a fixed configuration can provide a very small failure probability, such as 10.sup.-30. However, as clock frequencies increase there may not be enough settling time, and, for a given gate delay in the flip-flops, metastability can occur.
"For example, a typical flip-flop from a standard cell library may have a time-constant of two or three times a gate delay. For a 65 nm CMOS-process technology with a 20-ps gate delay, this time-constant may be 60 ps. In such a process, a two flip-flop synchronizer with a 100 MHz clock may have a failure probability of roughly 10.sup.-160 per synchronization event, which is unnecessarily conservative. However, with a 2 GHz clock, the failure probability may increase to 10.sup.-7, which is too large for many applications.
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