Pattern-aware memory technology built on top of Algorithmic Memory®
brings new solutions for datacom SoCs offering breakthrough
performance, power and area
“There are fundamental limitations with existing silicon technology that need to be overcome to enable terabit networking. As we crank up switching bandwidths into the terabit domain, the power consumption and heat generation alone make these solutions problematic for large scale data centers,” said
With its new pattern-aware technology, Renaissance for Datacom provides ultra-high performance multiport memories that were previously infeasible. Renaissance for Datacom is built on top of Memoir’s Renaissance 2X, 4X, and 10X families of embedded memories (based on Memoir’s award-winning Algorithmic Memory®), which offer deterministic, fully random access memory performance up to 10X memory operations per second (MOPS). Although many applications require deterministic memory performance, some only access memory in a specific pattern. Renaissance for Datacom recognizes four common memory patterns: allocation access used in packet buffers, read modify write access used to update memory in Netflow, policing and state tables, read add modify access used to maintain statistics counters, and sequential access used in multi-port FIFOs. The product includes four unique memory cores – Allocation, Update, Counter and Sequential memory core tailored for the above functions. These represent patterns that are commonly used, independent of the implementation, in a wide set of applications in the datacom SoCs.
Pattern-aware technology enables Renaissance for Datacom to extend memory performance all the way up to 16X MOPS for datacom SoCs. For instance, using an 8R8W allocation memory, developers can build a fully deterministic shared memory buffer with multi-terabit bandwidth in 28 nm process. Another key benefit of pattern-aware technology is its ability to reduce area, power and energy consumption. With a typical high performance SoC burning 80-100W, lowering the power and energy envelope is critical. Pattern-aware technology reflects a deeper understanding of the memory access patterns that in turn enables more intelligent management of memory. It enables fine grained power control of physical memory and reduces memory energy consumption by up to 70%, translating to up to 5% lower energy consumption on end systems.