Our news editors obtained a quote from the research, "Most of these timing errors occur on the signal distribution path due to the use of a large number of wiring cells but these effects are mostly ignored. Hence future circuit optimization tools should take both delay and jitter amount into account. Therefore, delay and jitter values of single and cascaded fundamental RSFQ wiring cells, namely Josephson transmission lines (JTL), splitters, and mergers, are analyzed. Also, low bias voltage driving of the circuit and the dependence on input signal frequency effects are observed."
According to the news editors, the research concluded: "Jitter and delay values depending on the aforementioned parameters for single gates and cascaded gates are reported."
For more information on this research see: Analysis of Delay and Jitter of Rapid Single Flux Quantum Wiring Cells.
The news editors report that additional information may be obtained by contacting
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