Patent number 8541311 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "During front end-of-the-line processing, a plurality of semiconductor devices (e.g., transistors, resistors, capacitors, and the like) are formed on a semiconductor wafer. During Back End-of-the-Line ('BEoL') processing, the semiconductor devices are interconnected to form a plurality of integrated circuits on the wafer, which are subsequently separated into individual die during wafer dicing. Interconnection of the semiconductor devices is accomplished via the formation of electrically-conductive features (e.g., conductive plugs and interconnect lines) in a plurality of dielectric layers successively deposited over the semiconductor devices during BEoL processing. For example, contact openings are etched in the first dielectric layer deposited directly over the semiconductor devices (commonly referred to as the 'pre-metal dielectric layer'), a conductive material (e.g., tungsten) is deposited into the contact openings, and the excess conductive material is removed by chemical mechanical planarization to produce a plurality of conductive plugs embedded in the pre-metal dielectric layer and in ohmic contact with electrically-active contact features of the semiconductor devices (e.g., doped regions, gate electrodes, etc.). Similarly, during fabrication of the BEoL metal levels, contact openings and trenches are etched within intermetal dielectric layers, filled with a conductive material (e.g., copper), and planarized to yield a plurality of conductive plugs and interconnect lines electrically interconnecting the semiconductor devices of the integrated circuits.
"Lithographical patterning techniques are conventionally utilized to create etch features in the dielectric layers formed during BEoL processing. However, conventional lithographical patterning techniques are inherently limited by resolution constraints. It can thus be difficult to reliably satisfy, within acceptable margins of error, circuit designs having relatively small critical dimensions and ultrafine pitch requirements (e.g., circuit designs for semiconductor generations equal to or less than 32 nm) utilizing conventional lithographical patterning techniques. As a specific example, during contact integration of an integrated circuit having closely spaced gates and contact features (e.g., doped regions), conventional lithographical patterning may be incapable of forming contact openings that are large enough to ensure reliable contact with the contact features of the semiconductor devices, while also reliably avoiding exposure of one or more of the gates through the pre-metal dielectric layer. If gate exposure occurs during contact etching, direct contact can occur between the exposed gate and the conducive metal with which the contact opening is filled. A short circuit may thus result, and overall wafer yield may be undesirably diminished. Although certain techniques have been developed to help reduce the risk of gate exposure during contact etching, such as imparting the contact openings with a tapered geometry and/or depositing an oxide shrinkage liner into the contact openings, such techniques add undesirable complexity, expense, and delay to BEoL processing and are not always effective at preventing gate exposure.
"There thus exists an ongoing demand to provide embodiments of a patterning and etching technique capable of forming etch features in dielectric layers during BEoL processing at resolutions exceeding those attainable utilizing conventional lithographical patterning techniques. It would be particularly desirable to provide embodiments of a patterning method that could be utilized to form high resolution contact openings in a pre-metal dielectric layer to decrease the likelihood of gate exposure during contact integration and thereby increase overall product yield. More generally, it would be desirable to provide embodiments of a process for fabricating an integrated circuit that incorporates such a high resolution patterning method. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended Claims, taken in conjunction with the accompanying Drawings and the foregoing Technical Field and Background."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein."
URL and more information on this patent, see: Chumakov, Dmytro. Integrated Circuit Fabrication Methods Utilizing Embedded Hardmask Layers for High Resolution Patterning. U.S. Patent Number 8541311, filed
Keywords for this news article include: Electronics, Semiconductor,
Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2013, NewsRx LLC
Most Popular Stories
- NSA Defends Global Cellphone Tracking Legality
- Ad Counts Rise in 2013 for Hispanic Magazines
- Networks Vie for U.S. Hispanic TV Viewers
- Apple Wants Samsung to Pay $22M for Patent Dispute Legal Bills
- Starbucks Gets Grinchy; No Gingerbread Lattes for Tampa Customers
- Apple Paid Its Lawyers More Than $60MM to Defeat Samsung in Court
- Economic Bright Spots Not a Sure Boost for President Obama
- Jobs Report Brings Cheer As Unemployment Drops to Five-year Low
- Top Websites for U.S. Hispanics
- US Consumer Borrowing Rose $18.2B in Oct.