Patent number 8543964 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Embodiments of the inventive subject matter generally relate to the design of an integrated circuit (IC) chip, and more specifically, to optimizing connection constraints in an integrated circuit design.
"Typically, large scale integrated circuits contain millions of logic gates. FIG. 1 shows the spatial structure of an existing IC chip, the bottom of the chip is a base layer consisting of transistors and the upper layer is a metal layer consisting of metal connections.
"In the design process of an integrated circuit, the first step is register transfer level (RTL) coding. The RTL coding is then encoded into a gate-level netlist containing devices and connections of chips by an IC design tool, such as a Synopsys.RTM. Design Compiler.RTM. tool. The process of encoding the RTL coding into a gate-level netlist may be referred to as synthesizing. Finally, operations for placement of chip devices and connecting the chip devices (also referred to as routing, wiring or lining) are performed.
"Based on the connection, the IC design tool will provide connection constraints before connecting, where the connection constraints include the length of the connection, the number of the metal layer at which the connection is located, and the width of the connection. In this manner, the IC design tool can automatically perform connections for the whole design in accordance with the requisite connection constraints. If the connection resource provided by a metal layer in a certain region of a chip (e.g., the amount of metal area required to create the requisite connections), is less than the requisite connection resource, the region of the chip is deemed to suffer from 'congestion' or is deemed to be 'congested.' Generally, a congestion matrix, a list of congestion values associated with different regions on the chip, or a congestion map can be used to describe the severity of the congestion and the position/location of the congestion on the chip.
"Back-end design of a general-purpose integrated circuit chip typically comprises two processes--timing closure and physical closure. Timing closure can refer to the process for ensuring that all the logical units in a circuit satisfy their corresponding predetermined timing requirements. The predetermined timing requirements can comprise setup time and hold time determined from a digital logic unit design library and/or other suitable timing requirements (e.g., based on the actual application) indicated by chip front-end developers. It is noted that if the predetermined timing requirements cannot be satisfied, the chips may not operate reliably (e.g., execute their logic operations as intended) at a predetermined temperature and voltage. Physical closure can refer to the process for ensuring that all the layout wirings on the chip satisfy a set of predetermined parameters known as Design Rule Checks (DRC). These design rules can be used to check whether all the logic connections are associated with corresponding connections at the physical level and whether the connection constraints are satisfied. It is noted that if the design rule checks are not satisfied, short circuits, open circuit, and other such connection errors can occur in the chips, causing malfunctioning (or unreliable operation) of the chips.
Most Popular Stories
- SpaceX's Satellite Launch Is 'Game-Changer'
- Reid Confident Congress to Pass Immigration Bill
- Maui Visitor Killed in Shark Attack
- Wisconsin Gov. Campaign Aide Fired Over Tweets
- Climate Change Early Warning System Urged
- Brazil Braces for Street Protests at World Cup
- Boehner Hires Immigration Reform Expert
- Sprint Not Moving Headquarters to California
- Gloom Settles on Markets Despite Strong Jobs Report
- Calif. Likes Christie, Says Tea Party's a Drag