Patent number 8555232 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "This disclosure is related to the field of integrated circuit design, and more particularly to systems and methods for wire routing.
"Physical design is a basic step in the creation of integrated circuits. During physical design, schematic representations of a circuit's various components (e.g., transistors, logic gates, logic cells, macros, etc.) are converted into geometric shapes that will later allow manufacturing of the circuit. During this process, once the various geometric shapes are placed on specific locations in the circuit, a 'wire routing' technique is used to connect components to each other in a manner that ensures the proper functioning of the circuit.
"Due to the high levels of integration and miniaturization present in the modern electronic chip, however, finding suitable ways to connect its various cells or components can be an incredibly complex task. As a result, wire routing operations may require that such cells and components have their physical pins, terminals, connectors, or ports (which would otherwise be relatively small in size) designed as larger or 'expanded' 'landing pads.' By using wider and/or longer landing pads, a wire router has more flexibility to make the specified connections, which in turn makes complex circuit designs more easily routable and saves computing time."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "This specification discloses systems and methods that may be employed in the design of integrated circuits (ICs), including, for example, in connection with electronic design automation (EDA) tools that include a wire routing module or similar functionality. In some embodiments, systems and methods may be implemented that allow an IC designer to design microprocessors, microcontrollers, memories, systems-on-a-chip (SoCs), application-specific integrated circuits (ASICs)--or any other type of digital or analog IC, as well as microelectromechanical systems (MEMS)--while reducing the IC's overall capacitance and its associated power consumption. Examples of electronic devices that may include one or more ICs designed using the techniques described herein include, but are not limited to, desktop computers, laptop computers, tablets, network appliances, mobile phones, personal digital assistants (PDAs), e-book readers, televisions, video game consoles, electronic control units, appliances, or any other electronic devices.
"In some embodiments, a method may include routing a wiring path between an output of a first circuit component and a virtual landing pad (VLP) that represents an input of a second circuit component. The VLP may be provided, for example, in the form of a first IC description or specification that defines a larger landing pad than the actual, physical pin, terminal, connector, or port that will ultimately be manufactured for the second circuit component. By using a VLP, a wire routing tool can more easily find a connection path between the first and second circuit components that satisfies one or more design constraints (e.g., signal timing, etc.).
"Moreover, use of the VLP by the wire routing tool may result in the output of the first circuit component being routed to an area that is not connected to the actual, planned terminal of the second circuit component (e.g., a non-conductive portion of the semiconductor substrate). Accordingly, the method may further include identifying the connection point and, in response to the connection point being separated from the actual terminal, completing the path from the connection point to the actual terminal. These operations may include using a second IC description or specification that defines the input of the second circuit component only as its actual, physical pin, instead of the larger VLP. After the path is completed, the method may further include, for example, verifying that the completed path (i.e., from the output of the first circuit component to the connection point and then to the actual terminal) still satisfies design constraints.
"In some embodiments, a routing software tool or module may be provided. The routing tool may be a standalone executable program or a part of a larger EDA software package. In some cases, the routing tool may receive manual commands from a user that allow it to perform one or more of the methods described herein. In other cases, the routing tool may be configured to perform 'autorouting' such that at least a portion of an IC's connections is routed without human intervention."
URL and more information on this patent, see: Vats, Suparn; Shrivastav, Gaurav. Wire Routing Using Virtual Landing Pads. U.S. Patent Number 8555232, filed
Keywords for this news article include: Software,
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